From: Lars Persson <lars.persson@axis.com>
To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org
Cc: mturquette@baylibre.com, sboyd@codeaurora.org,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux-kernel@vger.kernel.org, Lars Persson <larper@axis.com>
Subject: [PATCH 2/2] clk: add artpec-6 pll1 clock driver
Date: Thu, 11 Feb 2016 17:01:04 +0100 [thread overview]
Message-ID: <6d47cfe5ab7596e91a7fcc5647c5907cc12a4d83.1455206007.git.larper@axis.com> (raw)
In-Reply-To: <cover.1455206007.git.larper@axis.com>
In-Reply-To: <cover.1455206007.git.larper@axis.com>
The PLL1 clock is a fixed-factor clock with factors derived from boot
mode pins. This driver is a simple wrapper to register the fixed
factor clock according to the pin settings.
Signed-off-by: Lars Persson <larper@axis.com>
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-artpec6.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 71 insertions(+)
create mode 100644 drivers/clk/clk-artpec6.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b038e36..388f0cf 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -17,6 +17,7 @@ endif
# hardware specific clock types
# please keep this section sorted lexicographically by file/directory path name
+obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
diff --git a/drivers/clk/clk-artpec6.c b/drivers/clk/clk-artpec6.c
new file mode 100644
index 0000000..3664c44
--- /dev/null
+++ b/drivers/clk/clk-artpec6.c
@@ -0,0 +1,70 @@
+/*
+ * ARTPEC-6 clock initialization
+ *
+ * Copyright 2015 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+static void __init of_artpec6_pll1_setup(struct device_node *np)
+{
+ void __iomem *devstat;
+ struct clk *clk;
+ const char *clk_name = np->name;
+ const char *parent_name;
+ u32 pll_mode, pll_m, pll_n;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ devstat = of_iomap(np, 0);
+ if (devstat == NULL) {
+ pr_err("error to ioremap DEVSTAT\n");
+ return;
+ }
+
+ /* DEVSTAT register contains PLL settings */
+ pll_mode = (readl(devstat) >> 6) & 3;
+ iounmap(devstat);
+
+ /*
+ * pll1 settings are designed for different DDR speeds using a fixed
+ * 50MHz external clock. However, a different external clock could be
+ * used on different boards.
+ * CPU clock is half the DDR clock.
+ */
+ switch (pll_mode) {
+ case 0: /* DDR3-2133 mode */
+ pll_m = 4;
+ pll_n = 85;
+ break;
+ case 1: /* DDR3-1866 mode */
+ pll_m = 6;
+ pll_n = 112;
+ break;
+ case 2: /* DDR3-1600 mode */
+ pll_m = 4;
+ pll_n = 64;
+ break;
+ case 3: /* DDR3-1333 mode */
+ pll_m = 8;
+ pll_n = 106;
+ break;
+ }
+ /* ext_clk is defined in device tree */
+ clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
+ pll_n, pll_m);
+ if (IS_ERR(clk)) {
+ pr_err("%s not registered\n", clk_name);
+ return;
+ }
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(artpec6_pll1, "axis,artpec6-pll1-clock", of_artpec6_pll1_setup);
--
2.1.4
next prev parent reply other threads:[~2016-02-11 16:01 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-11 16:01 [PATCH 0/2] clk: Add Artpec-6 SoC support Lars Persson
2016-02-11 16:01 ` [PATCH 1/2] clk: add device tree binding for artpec-6 pll1 clock Lars Persson
2016-02-12 16:39 ` Rob Herring
2016-02-14 8:03 ` Lars Persson
2016-02-16 23:59 ` Michael Turquette
2016-02-17 10:29 ` Lars Persson
2016-02-18 0:35 ` Michael Turquette
2016-02-11 16:01 ` Lars Persson [this message]
2016-02-17 0:02 ` [PATCH 2/2] clk: add artpec-6 pll1 clock driver Michael Turquette
2016-02-17 10:30 ` Lars Persson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6d47cfe5ab7596e91a7fcc5647c5907cc12a4d83.1455206007.git.larper@axis.com \
--to=lars.persson@axis.com \
--cc=devicetree@vger.kernel.org \
--cc=galak@codeaurora.org \
--cc=ijc+devicetree@hellion.org.uk \
--cc=larper@axis.com \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mturquette@baylibre.com \
--cc=pawel.moll@arm.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).