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From: Patrice CHOTARD <patrice.chotard@foss.st.com>
To: <dillon.minfei@gmail.com>, <pierre-yves.mordret@foss.st.com>,
	<alain.volmat@foss.st.com>, <mcoquelin.stm32@gmail.com>,
	<alexandre.torgue@foss.st.com>, <sumit.semwal@linaro.org>,
	<christian.koenig@amd.com>, <mturquette@baylibre.com>
Cc: <sboyd@kernel.org>, <linux-i2c@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-media@vger.kernel.org>,
	<dri-devel@lists.freedesktop.org>,
	<linaro-mm-sig@lists.linaro.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH 3/4] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate
Date: Tue, 1 Jun 2021 14:48:10 +0200	[thread overview]
Message-ID: <6ecedc1d-3b80-0eba-a5f0-8feb3eae16cf@foss.st.com> (raw)
In-Reply-To: <1620990152-19255-4-git-send-email-dillon.minfei@gmail.com>

Hi Dillon

On 5/14/21 1:02 PM, dillon.minfei@gmail.com wrote:
> From: Dillon Min <dillon.minfei@gmail.com>
> 
> This is due to misuse ‘PLL_VCO_SAI' and'PLL_SAI' in clk-stm32f4.c
> 'PLL_SAI' is 2, 'PLL_VCO_SAI' is 7(defined in
> include/dt-bindings/clock/stm32fx-clock.h).
> 
> 'post_div' point to 'post_div_data[]', 'post_div->pll_num'
> is PLL_I2S or PLL_SAI.
> 
> 'clks[PLL_VCO_SAI]' has valid 'struct clk_hw* ' return
> from stm32f4_rcc_register_pll() but, at line 1777 of
> driver/clk/clk-stm32f4.c, use the 'clks[post_div->pll_num]',
> equal to 'clks[PLL_SAI]', this is invalid array member at that time.
> 
> Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs")
> Signed-off-by: Dillon Min <dillon.minfei@gmail.com>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> Link: https://lore.kernel.org/linux-arm-kernel/1590564453-24499-6-git-send-email-dillon.minfei@gmail.com/
> ---
>  drivers/clk/clk-stm32f4.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
> index 18117ce5ff85..42ca2dd86aea 100644
> --- a/drivers/clk/clk-stm32f4.c
> +++ b/drivers/clk/clk-stm32f4.c
> @@ -557,13 +557,13 @@ static const struct clk_div_table post_divr_table[] = {
>  
>  #define MAX_POST_DIV 3
>  static const struct stm32f4_pll_post_div_data  post_div_data[MAX_POST_DIV] = {
> -	{ CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
> +	{ CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
>  		CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
>  
> -	{ CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
> +	{ CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
>  		CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
>  
> -	{ NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
> +	{ NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
>  		STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
>  };
>  
> 
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

Thanks
Patrice

  reply	other threads:[~2021-06-01 12:48 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-14 11:02 [PATCH 0/4] Fix the i2c/clk bug of stm32 mcu platform dillon.minfei
2021-05-14 11:02 ` [PATCH 1/4] drm/panel: Add ilitek ili9341 panel driver dillon.minfei
2021-05-31 13:15   ` Patrice CHOTARD
2021-05-31 13:39     ` Dillon Min
2021-06-01  2:31       ` Dillon Min
2021-05-14 11:02 ` [PATCH 2/4] i2c: stm32f4: Fix stmpe811 get xyz data timeout issue dillon.minfei
2021-06-01 11:43   ` Patrice CHOTARD
2021-06-01 11:58     ` Dillon Min
2021-05-14 11:02 ` [PATCH 3/4] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate dillon.minfei
2021-06-01 12:48   ` Patrice CHOTARD [this message]
2021-05-14 11:02 ` [PATCH 4/4] clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after kernel startup dillon.minfei
2021-06-01 12:51   ` Patrice CHOTARD
2021-05-28  6:01 ` [PATCH 0/4] Fix the i2c/clk bug of stm32 mcu platform Dillon Min
2021-05-31 13:20 ` Patrice CHOTARD
2021-05-31 13:38   ` Dillon Min
2021-05-31 13:50     ` Patrice CHOTARD
2021-05-31 14:29       ` Dillon Min
2021-05-31 14:58         ` Patrice CHOTARD
2021-06-01  3:28           ` Dillon Min
2021-06-01  8:00             ` Patrice CHOTARD

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