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[86.26.103.58]) by smtp.googlemail.com with ESMTPSA id x18sm41464215wrw.17.2022.02.18.05.24.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Feb 2022 05:24:46 -0800 (PST) Message-ID: <6f3ff8f3-82fb-1bb1-d854-bb48f1ea9b1d@linaro.org> Date: Fri, 18 Feb 2022 13:24:45 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v3 3/4] nvmem: core: Fix a conflict between MTD and NVMEM on wp-gpios property Content-Language: en-US To: Christophe Kerello , miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, p.yadav@ti.com Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, devicetree@vger.kernel.org, chenshumin86@sina.com, stable@vger.kernel.org References: <20220217144755.270679-1-christophe.kerello@foss.st.com> <20220217144755.270679-4-christophe.kerello@foss.st.com> From: Srinivas Kandagatla In-Reply-To: <20220217144755.270679-4-christophe.kerello@foss.st.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/02/2022 14:47, Christophe Kerello wrote: > Wp-gpios property can be used on NVMEM nodes and the same property can > be also used on MTD NAND nodes. In case of the wp-gpios property is > defined at NAND level node, the GPIO management is done at NAND driver > level. Write protect is disabled when the driver is probed or resumed > and is enabled when the driver is released or suspended. > > When no partitions are defined in the NAND DT node, then the NAND DT node > will be passed to NVMEM framework. If wp-gpios property is defined in > this node, the GPIO resource is taken twice and the NAND controller > driver fails to probe. > > It would be possible to set config->wp_gpio at MTD level before calling > nvmem_register function but NVMEM framework will toggle this GPIO on > each write when this GPIO should only be controlled at NAND level driver > to ensure that the Write Protect has not been enabled. > > A way to fix this conflict is to add a new boolean flag in nvmem_config > named ignore_wp. In case ignore_wp is set, the GPIO resource will > be managed by the provider. > > Fixes: 2a127da461a9 ("nvmem: add support for the write-protect pin") > Signed-off-by: Christophe Kerello > Cc: stable@vger.kernel.org > --- > Changes in v3: > - add a fixes tag. > - rename skip_wp_gpio by ignore_wp in nvmen_config. Applied thanks, --srini > > Changes in v2: > - rework the proposal done to fix a conflict between MTD and NVMEM on > wp-gpios property. > > drivers/nvmem/core.c | 2 +- > include/linux/nvmem-provider.h | 4 +++- > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c > index 23a38dcf0fc4..9fd1602b539d 100644 > --- a/drivers/nvmem/core.c > +++ b/drivers/nvmem/core.c > @@ -771,7 +771,7 @@ struct nvmem_device *nvmem_register(const struct nvmem_config *config) > > if (config->wp_gpio) > nvmem->wp_gpio = config->wp_gpio; > - else > + else if (!config->ignore_wp) > nvmem->wp_gpio = gpiod_get_optional(config->dev, "wp", > GPIOD_OUT_HIGH); > if (IS_ERR(nvmem->wp_gpio)) { > diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h > index 98efb7b5660d..c9a3ac9efeaa 100644 > --- a/include/linux/nvmem-provider.h > +++ b/include/linux/nvmem-provider.h > @@ -70,7 +70,8 @@ struct nvmem_keepout { > * @word_size: Minimum read/write access granularity. > * @stride: Minimum read/write access stride. > * @priv: User context passed to read/write callbacks. > - * @wp-gpio: Write protect pin > + * @wp-gpio: Write protect pin > + * @ignore_wp: Write Protect pin is managed by the provider. > * > * Note: A default "nvmem" name will be assigned to the device if > * no name is specified in its configuration. In such case "" is > @@ -92,6 +93,7 @@ struct nvmem_config { > enum nvmem_type type; > bool read_only; > bool root_only; > + bool ignore_wp; > struct device_node *of_node; > bool no_of_node; > nvmem_reg_read_t reg_read;