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* [PATCH v5 00/10] ASPEED sgpio driver enhancement.
@ 2021-06-08 10:25 Steven Lee
  2021-06-08 10:25 ` [PATCH v5 01/10] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml Steven Lee
                   ` (10 more replies)
  0 siblings, 11 replies; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.

For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed-g6 dtsi to support the enhanced sgpio.
- Define max number of gpio pins in ast2600 platform data. Old chip
  uses the original hardcoded value.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins.
- Support wdt reset tolerance.
- Fix irq_chip issues which causes multiple sgpio devices use the same
  irq_chip data.
- Replace all of_*() APIs with device_*().

Changes from v4:
* Remove ngpios from dtsi
* Add ast2400 and ast2500 platform data.
* Remove unused macros.
* Add ngpios check in a separate patch.
* Fix coding style issues.

Changes from v3:
* Split dt-bindings patch to 2 patches
* Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
* Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
* Correct the typo in commit messages.
* Fix coding style issues.
* Replace all of_*() APIs with device_*().

Changes from v2:
* Remove maximum/minimum of ngpios from bindings.
* Remove max-ngpios from bindings and dtsi.
* Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
  driver.
* Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
  number of available gpio pins are different.
* Modify functions to pass aspeed_sgpio struct instead of passing
  max_ngpios.
* Split sgpio driver patch to 3 patches

Changes from v1:
* Fix yaml format issues.
* Fix issues reported by kernel test robot.

Please help to review.

Thanks,
Steven

Steven Lee (10):
  dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
  dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.
  ARM: dts: aspeed-g6: Add SGPIO node.
  ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
  gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
  gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data.
  gpio: gpio-aspeed-sgpio: Add set_config function
  gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
  gpio: gpio-aspeed-sgpio: Use generic device property APIs
  gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.

 .../bindings/gpio/aspeed,sgpio.yaml           |  78 +++++++
 .../devicetree/bindings/gpio/sgpio-aspeed.txt |  46 ----
 arch/arm/boot/dts/aspeed-g5.dtsi              |   1 -
 arch/arm/boot/dts/aspeed-g6.dtsi              |  28 +++
 drivers/gpio/gpio-aspeed-sgpio.c              | 206 ++++++++++++------
 5 files changed, 248 insertions(+), 111 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
 delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt

-- 
2.17.1


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v5 01/10] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
@ 2021-06-08 10:25 ` Steven Lee
  2021-06-09  0:42   ` Andrew Jeffery
  2021-06-10 16:18   ` Rob Herring
  2021-06-08 10:25 ` [PATCH v5 02/10] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles Steven Lee
                   ` (9 subsequent siblings)
  10 siblings, 2 replies; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

sgpio-aspeed bindings should be converted to yaml format.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 .../bindings/gpio/aspeed,sgpio.yaml           | 75 +++++++++++++++++++
 .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ------------
 2 files changed, 75 insertions(+), 46 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
 delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt

diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
new file mode 100644
index 000000000000..b2ae211411ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed SGPIO controller
+
+maintainers:
+  - Andrew Jeffery <andrew@aj.id.au>
+
+description:
+  This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
+  featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
+  support the following options
+  - Support interrupt option for each input port and various interrupt
+    sensitivity option (level-high, level-low, edge-high, edge-low)
+  - Support reset tolerance option for each output port
+  - Directly connected to APB bus and its shift clock is from APB bus clock
+    divided by a programmable value.
+  - Co-work with external signal-chained TTL components (74LV165/74LV595)
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2400-sgpio
+      - aspeed,ast2500-sgpio
+
+  reg:
+    maxItems: 1
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  clocks:
+    maxItems: 1
+
+  ngpios: true
+
+  bus-frequency: true
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - '#gpio-cells'
+  - interrupts
+  - interrupt-controller
+  - ngpios
+  - clocks
+  - bus-frequency
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/aspeed-clock.h>
+    sgpio: sgpio@1e780200 {
+        #gpio-cells = <2>;
+        compatible = "aspeed,ast2500-sgpio";
+        gpio-controller;
+        interrupts = <40>;
+        reg = <0x1e780200 0x0100>;
+        clocks = <&syscon ASPEED_CLK_APB>;
+        interrupt-controller;
+        ngpios = <80>;
+        bus-frequency = <12000000>;
+    };
diff --git a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
deleted file mode 100644
index be329ea4794f..000000000000
--- a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Aspeed SGPIO controller Device Tree Bindings
---------------------------------------------
-
-This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
-featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
-support the following options:
-- Support interrupt option for each input port and various interrupt
-  sensitivity option (level-high, level-low, edge-high, edge-low)
-- Support reset tolerance option for each output port
-- Directly connected to APB bus and its shift clock is from APB bus clock
-  divided by a programmable value.
-- Co-work with external signal-chained TTL components (74LV165/74LV595)
-
-Required properties:
-
-- compatible : Should be one of
-  "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
-- #gpio-cells : Should be 2, see gpio.txt
-- reg : Address and length of the register set for the device
-- gpio-controller : Marks the device node as a GPIO controller
-- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
-- interrupt-controller : Mark the GPIO controller as an interrupt-controller
-- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
-  2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
-  output. Up to 80 pins, must be a multiple of 8.
-- clocks : A phandle to the APB clock for SGPM clock division
-- bus-frequency : SGPM CLK frequency
-
-The sgpio and interrupt properties are further described in their respective
-bindings documentation:
-
-- Documentation/devicetree/bindings/gpio/gpio.txt
-- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-  Example:
-	sgpio: sgpio@1e780200 {
-		#gpio-cells = <2>;
-		compatible = "aspeed,ast2500-sgpio";
-		gpio-controller;
-		interrupts = <40>;
-		reg = <0x1e780200 0x0100>;
-		clocks = <&syscon ASPEED_CLK_APB>;
-		interrupt-controller;
-		ngpios = <8>;
-		bus-frequency = <12000000>;
-	};
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH v5 02/10] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
  2021-06-08 10:25 ` [PATCH v5 01/10] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml Steven Lee
@ 2021-06-08 10:25 ` Steven Lee
  2021-06-10 16:23   ` Rob Herring
  2021-06-08 10:25 ` [PATCH v5 03/10] ARM: dts: aspeed-g6: Add SGPIO node Steven Lee
                   ` (8 subsequent siblings)
  10 siblings, 1 reply; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins. Add ast2600-sgpiom0-80 and ast2600-sgpiom-128 compatibles
and update descriptions to introduce the max number of available gpio
pins that AST2600 supported.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
index b2ae211411ff..0e42eded3c1e 100644
--- a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
@@ -10,9 +10,10 @@ maintainers:
   - Andrew Jeffery <andrew@aj.id.au>
 
 description:
-  This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
-  featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
-  support the following options
+  This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
+  AST2600 have two sgpio master one with 128 pins another one with 80 pins,
+  AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
+  GPIO pins can be programmed to support the following options
   - Support interrupt option for each input port and various interrupt
     sensitivity option (level-high, level-low, edge-high, edge-low)
   - Support reset tolerance option for each output port
@@ -25,6 +26,8 @@ properties:
     enum:
       - aspeed,ast2400-sgpio
       - aspeed,ast2500-sgpio
+      - aspeed,ast2600-sgpiom-80
+      - aspeed,ast2600-sgpiom-128
 
   reg:
     maxItems: 1
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH v5 03/10] ARM: dts: aspeed-g6: Add SGPIO node.
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
  2021-06-08 10:25 ` [PATCH v5 01/10] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml Steven Lee
  2021-06-08 10:25 ` [PATCH v5 02/10] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles Steven Lee
@ 2021-06-08 10:25 ` Steven Lee
  2021-06-09  0:43   ` Andrew Jeffery
  2021-06-08 10:25 ` [PATCH v5 04/10] ARM: dts: aspeed-g5: Remove ngpios from sgpio node Steven Lee
                   ` (7 subsequent siblings)
  10 siblings, 1 reply; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
with 80 pins.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index f96607b7b4e2..c55baaf94314 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -377,6 +377,34 @@
 				#interrupt-cells = <2>;
 			};
 
+			sgpiom0: sgpiom@1e780500 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpiom-128";
+				reg = <0x1e780500 0x100>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+				interrupt-controller;
+				bus-frequency = <12000000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sgpm1_default>;
+				status = "disabled";
+			};
+
+			sgpiom1: sgpiom@1e780600 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpiom-80";
+				reg = <0x1e780600 0x100>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+				interrupt-controller;
+				bus-frequency = <12000000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sgpm2_default>;
+				status = "disabled";
+			};
+
 			gpio1: gpio@1e780800 {
 				#gpio-cells = <2>;
 				gpio-controller;
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH v5 04/10] ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
                   ` (2 preceding siblings ...)
  2021-06-08 10:25 ` [PATCH v5 03/10] ARM: dts: aspeed-g6: Add SGPIO node Steven Lee
@ 2021-06-08 10:25 ` Steven Lee
  2021-06-09  0:45   ` Andrew Jeffery
  2021-06-08 10:25 ` [PATCH v5 05/10] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support Steven Lee
                   ` (6 subsequent siblings)
  10 siblings, 1 reply; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

Remove ngpios property from sgpio node as it should be defined in the
platform dts.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d733c1f161c1..2701a58a5ab7 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -351,7 +351,6 @@
 				reg = <0x1e780200 0x0100>;
 				clocks = <&syscon ASPEED_CLK_APB>;
 				interrupt-controller;
-				ngpios = <8>;
 				bus-frequency = <12000000>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_sgpm_default>;
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH v5 05/10] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
                   ` (3 preceding siblings ...)
  2021-06-08 10:25 ` [PATCH v5 04/10] ARM: dts: aspeed-g5: Remove ngpios from sgpio node Steven Lee
@ 2021-06-08 10:25 ` Steven Lee
  2021-06-09  0:52   ` Andrew Jeffery
  2021-06-08 10:25 ` [PATCH v5 06/10] gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data Steven Lee
                   ` (5 subsequent siblings)
  10 siblings, 1 reply; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins.
In the current driver, the maximum number of gpio pins of SoC is hardcoded
as 80 and the gpio pin count mask for GPIO Configuration register is
hardcode as GENMASK(9,6). In addition, some functions use the hardcoded
value to calculate the gpio offset.
The patch adds ast2600 compatibles and platform data that includes the
max number of gpio pins supported by ast2600 and gpio pin count mask for
GPIO Configuration register.
The patch also modifies some functions to pass aspeed_sgpio struct for
calculating gpio offset without using the hardcoded value.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 107 +++++++++++++++++++++----------
 1 file changed, 73 insertions(+), 34 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 64e54f8c30d2..ea20a0127748 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -34,6 +34,12 @@
 #define ASPEED_SGPIO_PINS_MASK		GENMASK(9, 6)
 #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
 #define ASPEED_SGPIO_ENABLE		BIT(0)
+#define ASPEED_SGPIO_PINS_SHIFT		6
+
+struct aspeed_sgpio_pdata {
+	const u32 pin_mask;
+	int max_ngpios;
+};
 
 struct aspeed_sgpio {
 	struct gpio_chip chip;
@@ -41,6 +47,7 @@ struct aspeed_sgpio {
 	spinlock_t lock;
 	void __iomem *base;
 	int irq;
+	int max_ngpios;
 	int n_sgpio;
 };
 
@@ -75,7 +82,13 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
 		.val_regs = 0x0038,
 		.rdata_reg = 0x0078,
 		.irq_regs = 0x003C,
-		.names = { "I", "J" },
+		.names = { "I", "J", "K", "L" },
+	},
+	{
+		.val_regs = 0x0090,
+		.rdata_reg = 0x007C,
+		.irq_regs = 0x0094,
+		.names = { "M", "N", "O", "P" },
 	},
 };
 
@@ -121,15 +134,15 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
 	}
 }
 
-#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
-#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
-#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
+#define GPIO_BANK(gpio, x)    (((x) % (gpio)->max_ngpios) >> 5)
+#define GPIO_OFFSET(x)        ((x) & GENMASK(4, 0))
+#define GPIO_BIT(gpio, x)     BIT(GPIO_OFFSET((x) % (gpio)->max_ngpios))
 
-static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
+static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, const struct aspeed_sgpio *gpio)
 {
 	unsigned int bank;
 
-	bank = GPIO_BANK(offset);
+	bank = GPIO_BANK(gpio, offset);
 
 	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
 	return &aspeed_sgpio_banks[bank];
@@ -139,18 +152,19 @@ static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
 		unsigned long *valid_mask, unsigned int ngpios)
 {
 	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
+	int max_ngpios = sgpio->max_ngpios;
 	int n = sgpio->n_sgpio;
-	int c = SGPIO_OUTPUT_OFFSET - n;
+	int c = max_ngpios - n;
 
-	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
+	WARN_ON(ngpios < max_ngpios * 2);
 
 	/* input GPIOs in the lower range */
 	bitmap_set(valid_mask, 0, n);
 	bitmap_clear(valid_mask, n, c);
 
-	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
-	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
-	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
+	/* output GPIOS above max_ngpios */
+	bitmap_set(valid_mask, max_ngpios, n);
+	bitmap_clear(valid_mask, max_ngpios + n, c);
 
 	return 0;
 }
@@ -161,30 +175,30 @@ static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
 	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
 	int n = sgpio->n_sgpio;
 
-	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
+	WARN_ON(ngpios < sgpio->max_ngpios * 2);
 
 	/* input GPIOs in the lower range */
 	bitmap_set(valid_mask, 0, n);
 	bitmap_clear(valid_mask, n, ngpios - n);
 }
 
-static bool aspeed_sgpio_is_input(unsigned int offset)
+static bool aspeed_sgpio_is_input(unsigned int offset, const struct aspeed_sgpio *gpio)
 {
-	return offset < SGPIO_OUTPUT_OFFSET;
+	return offset < gpio->max_ngpios;
 }
 
 static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
 {
 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
-	const struct aspeed_sgpio_bank *bank = to_bank(offset);
+	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
 	unsigned long flags;
 	enum aspeed_sgpio_reg reg;
 	int rc = 0;
 
 	spin_lock_irqsave(&gpio->lock, flags);
 
-	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
-	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
+	reg = aspeed_sgpio_is_input(offset, gpio) ? reg_val : reg_rdata;
+	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(gpio, offset));
 
 	spin_unlock_irqrestore(&gpio->lock, flags);
 
@@ -194,11 +208,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
 static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
 {
 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
-	const struct aspeed_sgpio_bank *bank = to_bank(offset);
+	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
 	void __iomem *addr_r, *addr_w;
 	u32 reg = 0;
 
-	if (aspeed_sgpio_is_input(offset))
+	if (aspeed_sgpio_is_input(offset, gpio))
 		return -EINVAL;
 
 	/* Since this is an output, read the cached value from rdata, then
@@ -209,9 +223,9 @@ static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
 	reg = ioread32(addr_r);
 
 	if (val)
-		reg |= GPIO_BIT(offset);
+		reg |= GPIO_BIT(gpio, offset);
 	else
-		reg &= ~GPIO_BIT(offset);
+		reg &= ~GPIO_BIT(gpio, offset);
 
 	iowrite32(reg, addr_w);
 
@@ -232,7 +246,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
 
 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
 {
-	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
+	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+
+	return aspeed_sgpio_is_input(offset, gpio) ? 0 : -EINVAL;
 }
 
 static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
@@ -253,7 +269,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int v
 
 static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 {
-	return !!aspeed_sgpio_is_input(offset);
+	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+
+	return !!aspeed_sgpio_is_input(offset, gpio);
 }
 
 static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
@@ -268,8 +286,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
 	WARN_ON(!internal);
 
 	*gpio = internal;
-	*bank = to_bank(*offset);
-	*bit = GPIO_BIT(*offset);
+	*bank = to_bank(*offset, internal);
+	*bit = GPIO_BIT(internal, *offset);
 }
 
 static void aspeed_sgpio_irq_ack(struct irq_data *d)
@@ -466,9 +484,21 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 	return 0;
 }
 
+static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
+	.max_ngpios = 128,
+	.pin_mask = GENMASK(10, 6),
+};
+
+static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
+	.max_ngpios = 80,
+	.pin_mask = GENMASK(10, 6),
+};
+
 static const struct of_device_id aspeed_sgpio_of_table[] = {
 	{ .compatible = "aspeed,ast2400-sgpio" },
 	{ .compatible = "aspeed,ast2500-sgpio" },
+	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = &ast2600_sgpiom_128_pdata, },
+	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = &ast2600_sgpiom_80_pdata, },
 	{}
 };
 
@@ -476,10 +506,11 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
 
 static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 {
+	u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
+	const struct aspeed_sgpio_pdata *pdata;
 	struct aspeed_sgpio *gpio;
-	u32 nr_gpios, sgpio_freq, sgpio_clk_div;
-	int rc;
 	unsigned long apb_freq;
+	int rc;
 
 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 	if (!gpio)
@@ -489,13 +520,22 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	if (IS_ERR(gpio->base))
 		return PTR_ERR(gpio->base);
 
+	pdata = device_get_match_data(&pdev->dev);
+	if (pdata) {
+		gpio->max_ngpios = pdata->max_ngpios;
+		pin_mask = pdata->pin_mask;
+	} else {
+		gpio->max_ngpios = MAX_NR_HW_SGPIO;
+		pin_mask = ASPEED_SGPIO_PINS_MASK;
+	}
+
 	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Could not read ngpios property\n");
 		return -EINVAL;
-	} else if (nr_gpios > MAX_NR_HW_SGPIO) {
+	} else if (nr_gpios > gpio->max_ngpios) {
 		dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
-			MAX_NR_HW_SGPIO, nr_gpios);
+			gpio->max_ngpios, nr_gpios);
 		return -EINVAL;
 	}
 	gpio->n_sgpio = nr_gpios;
@@ -531,15 +571,14 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	if (sgpio_clk_div > (1 << 16) - 1)
 		return -EINVAL;
 
-	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
-		  FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
-		  ASPEED_SGPIO_ENABLE,
-		  gpio->base + ASPEED_SGPIO_CTRL);
+	gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
+	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
+		  ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
 
 	spin_lock_init(&gpio->lock);
 
 	gpio->chip.parent = &pdev->dev;
-	gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2;
+	gpio->chip.ngpio = gpio->max_ngpios * 2;
 	gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
 	gpio->chip.direction_input = aspeed_sgpio_dir_in;
 	gpio->chip.direction_output = aspeed_sgpio_dir_out;
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH v5 06/10] gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data.
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
                   ` (4 preceding siblings ...)
  2021-06-08 10:25 ` [PATCH v5 05/10] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support Steven Lee
@ 2021-06-08 10:25 ` Steven Lee
  2021-06-09  0:55   ` Andrew Jeffery
  2021-06-08 10:25 ` [PATCH v5 07/10] gpio: gpio-aspeed-sgpio: Add set_config function Steven Lee
                   ` (4 subsequent siblings)
  10 siblings, 1 reply; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

We use platform data to store GPIO pin mask and the max number of
available GPIO pins for AST2600.
Refactor driver to also add the platform data for AST2400/AST2500 and
remove unused MAX_NR_HW_SGPIO and ASPEED_SGPIO_PINS_MASK macros.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 34 +++++++++++---------------------
 1 file changed, 12 insertions(+), 22 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index ea20a0127748..7d0a4f6fd9d1 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -17,21 +17,8 @@
 #include <linux/spinlock.h>
 #include <linux/string.h>
 
-/*
- * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
- * slots within the clocked serial GPIO data). Since each HW GPIO is both an
- * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
- * device.
- *
- * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
- * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
- */
-#define MAX_NR_HW_SGPIO			80
-#define SGPIO_OUTPUT_OFFSET		MAX_NR_HW_SGPIO
-
 #define ASPEED_SGPIO_CTRL		0x54
 
-#define ASPEED_SGPIO_PINS_MASK		GENMASK(9, 6)
 #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
 #define ASPEED_SGPIO_ENABLE		BIT(0)
 #define ASPEED_SGPIO_PINS_SHIFT		6
@@ -484,6 +471,11 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 	return 0;
 }
 
+static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
+	.max_ngpios = 80,
+	.pin_mask = GENMASK(9, 6),
+};
+
 static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
 	.max_ngpios = 128,
 	.pin_mask = GENMASK(10, 6),
@@ -495,8 +487,8 @@ static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
 };
 
 static const struct of_device_id aspeed_sgpio_of_table[] = {
-	{ .compatible = "aspeed,ast2400-sgpio" },
-	{ .compatible = "aspeed,ast2500-sgpio" },
+	{ .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
+	{ .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
 	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = &ast2600_sgpiom_128_pdata, },
 	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = &ast2600_sgpiom_80_pdata, },
 	{}
@@ -521,13 +513,11 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 		return PTR_ERR(gpio->base);
 
 	pdata = device_get_match_data(&pdev->dev);
-	if (pdata) {
-		gpio->max_ngpios = pdata->max_ngpios;
-		pin_mask = pdata->pin_mask;
-	} else {
-		gpio->max_ngpios = MAX_NR_HW_SGPIO;
-		pin_mask = ASPEED_SGPIO_PINS_MASK;
-	}
+	if (!pdata)
+		return -EINVAL;
+
+	gpio->max_ngpios = pdata->max_ngpios;
+	pin_mask = pdata->pin_mask;
 
 	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
 	if (rc < 0) {
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH v5 07/10] gpio: gpio-aspeed-sgpio: Add set_config function
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
                   ` (5 preceding siblings ...)
  2021-06-08 10:25 ` [PATCH v5 06/10] gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data Steven Lee
@ 2021-06-08 10:25 ` Steven Lee
  2021-06-08 10:25 ` [PATCH v5 08/10] gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct Steven Lee
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

AST SoC supports *retain pin state* function when wdt reset.
The patch adds set_config function for handling sgpio reset tolerance
register.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 54 +++++++++++++++++++++++++++++---
 1 file changed, 50 insertions(+), 4 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 7d0a4f6fd9d1..31475846c5fc 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -39,9 +39,10 @@ struct aspeed_sgpio {
 };
 
 struct aspeed_sgpio_bank {
-	uint16_t    val_regs;
-	uint16_t    rdata_reg;
-	uint16_t    irq_regs;
+	u16    val_regs;
+	u16    rdata_reg;
+	u16    irq_regs;
+	u16    tolerance_regs;
 	const char  names[4][3];
 };
 
@@ -57,24 +58,28 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
 		.val_regs = 0x0000,
 		.rdata_reg = 0x0070,
 		.irq_regs = 0x0004,
+		.tolerance_regs = 0x0018,
 		.names = { "A", "B", "C", "D" },
 	},
 	{
 		.val_regs = 0x001C,
 		.rdata_reg = 0x0074,
 		.irq_regs = 0x0020,
+		.tolerance_regs = 0x0034,
 		.names = { "E", "F", "G", "H" },
 	},
 	{
 		.val_regs = 0x0038,
 		.rdata_reg = 0x0078,
 		.irq_regs = 0x003C,
+		.tolerance_regs = 0x0050,
 		.names = { "I", "J", "K", "L" },
 	},
 	{
 		.val_regs = 0x0090,
 		.rdata_reg = 0x007C,
 		.irq_regs = 0x0094,
+		.tolerance_regs = 0x00A8,
 		.names = { "M", "N", "O", "P" },
 	},
 };
@@ -87,6 +92,7 @@ enum aspeed_sgpio_reg {
 	reg_irq_type1,
 	reg_irq_type2,
 	reg_irq_status,
+	reg_tolerance,
 };
 
 #define GPIO_VAL_VALUE      0x00
@@ -115,6 +121,8 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
 	case reg_irq_status:
 		return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
+	case reg_tolerance:
+		return gpio->base + bank->tolerance_regs;
 	default:
 		/* acturally if code runs to here, it's an error case */
 		BUG();
@@ -476,6 +484,44 @@ static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
 	.pin_mask = GENMASK(9, 6),
 };
 
+static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
+					unsigned int offset, bool enable)
+{
+	struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
+	unsigned long flags;
+	void __iomem *reg;
+	u32 val;
+
+	reg = bank_reg(gpio, to_bank(offset, gpio), reg_tolerance);
+
+	spin_lock_irqsave(&gpio->lock, flags);
+
+	val = readl(reg);
+
+	if (enable)
+		val |= GPIO_BIT(gpio, offset);
+	else
+		val &= ~GPIO_BIT(gpio, offset);
+
+	writel(val, reg);
+
+	spin_unlock_irqrestore(&gpio->lock, flags);
+
+	return 0;
+}
+
+static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
+				   unsigned long config)
+{
+	unsigned long param = pinconf_to_config_param(config);
+	u32 arg = pinconf_to_config_argument(config);
+
+	if (param == PIN_CONFIG_PERSIST_STATE)
+		return aspeed_sgpio_reset_tolerance(chip, offset, arg);
+
+	return -ENOTSUPP;
+}
+
 static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
 	.max_ngpios = 128,
 	.pin_mask = GENMASK(10, 6),
@@ -577,7 +623,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	gpio->chip.free = NULL;
 	gpio->chip.get = aspeed_sgpio_get;
 	gpio->chip.set = aspeed_sgpio_set;
-	gpio->chip.set_config = NULL;
+	gpio->chip.set_config = aspeed_sgpio_set_config;
 	gpio->chip.label = dev_name(&pdev->dev);
 	gpio->chip.base = -1;
 
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH v5 08/10] gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
                   ` (6 preceding siblings ...)
  2021-06-08 10:25 ` [PATCH v5 07/10] gpio: gpio-aspeed-sgpio: Add set_config function Steven Lee
@ 2021-06-08 10:25 ` Steven Lee
  2021-06-08 10:25 ` [PATCH v5 09/10] gpio: gpio-aspeed-sgpio: Use generic device property APIs Steven Lee
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

The current design initializes irq->chip from a global irqchip struct,
which causes multiple sgpio devices use the same irq_chip.
The patch moves irq_chip to aspeed_sgpio struct for initializing
irq_chip from their private gpio struct.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 31475846c5fc..38f4900d84bd 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -30,6 +30,7 @@ struct aspeed_sgpio_pdata {
 
 struct aspeed_sgpio {
 	struct gpio_chip chip;
+	struct irq_chip intc;
 	struct clk *pclk;
 	spinlock_t lock;
 	void __iomem *base;
@@ -425,14 +426,6 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
 	chained_irq_exit(ic, desc);
 }
 
-static struct irq_chip aspeed_sgpio_irqchip = {
-	.name       = "aspeed-sgpio",
-	.irq_ack    = aspeed_sgpio_irq_ack,
-	.irq_mask   = aspeed_sgpio_irq_mask,
-	.irq_unmask = aspeed_sgpio_irq_unmask,
-	.irq_set_type   = aspeed_sgpio_set_type,
-};
-
 static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 				   struct platform_device *pdev)
 {
@@ -455,8 +448,14 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
 		iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
 	}
 
+	gpio->intc.name = dev_name(&pdev->dev);
+	gpio->intc.irq_ack = aspeed_sgpio_irq_ack;
+	gpio->intc.irq_mask = aspeed_sgpio_irq_mask;
+	gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;
+	gpio->intc.irq_set_type = aspeed_sgpio_set_type;
+
 	irq = &gpio->chip.irq;
-	irq->chip = &aspeed_sgpio_irqchip;
+	irq->chip = &gpio->intc;
 	irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
 	irq->handler = handle_bad_irq;
 	irq->default_type = IRQ_TYPE_NONE;
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH v5 09/10] gpio: gpio-aspeed-sgpio: Use generic device property APIs
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
                   ` (7 preceding siblings ...)
  2021-06-08 10:25 ` [PATCH v5 08/10] gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct Steven Lee
@ 2021-06-08 10:25 ` Steven Lee
  2021-06-08 10:25 ` [PATCH v5 10/10] gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8 Steven Lee
  2021-06-09 10:54 ` [PATCH v5 00/10] ASPEED sgpio driver enhancement Linus Walleij
  10 siblings, 0 replies; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

Replace all of_property_read_u32() with device_property_read_u32().

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 38f4900d84bd..f1e40486d401 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -564,7 +564,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	gpio->max_ngpios = pdata->max_ngpios;
 	pin_mask = pdata->pin_mask;
 
-	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
+	rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Could not read ngpios property\n");
 		return -EINVAL;
@@ -575,7 +575,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 	}
 	gpio->n_sgpio = nr_gpios;
 
-	rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
+	rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);
 	if (rc < 0) {
 		dev_err(&pdev->dev, "Could not read bus-frequency property\n");
 		return -EINVAL;
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [PATCH v5 10/10] gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
                   ` (8 preceding siblings ...)
  2021-06-08 10:25 ` [PATCH v5 09/10] gpio: gpio-aspeed-sgpio: Use generic device property APIs Steven Lee
@ 2021-06-08 10:25 ` Steven Lee
  2021-06-09  0:56   ` Andrew Jeffery
  2021-06-09 10:54 ` [PATCH v5 00/10] ASPEED sgpio driver enhancement Linus Walleij
  10 siblings, 1 reply; 31+ messages in thread
From: Steven Lee @ 2021-06-08 10:25 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	Andrew Jeffery, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

Add an else-if condition in the probe function to check whether ngpios is
multiple of 8.
Per AST datasheet, numbers of available serial GPIO pins in Serial GPIO
Configuration Register must be n bytes. For instance, if n = 1, it means
AST SoC supports 8 GPIO pins.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index f1e40486d401..1a3fcc721664 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -572,6 +572,10 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
 			gpio->max_ngpios, nr_gpios);
 		return -EINVAL;
+	} else if (nr_gpios % 8) {
+		dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
+			nr_gpios);
+		return -EINVAL;
 	}
 	gpio->n_sgpio = nr_gpios;
 
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 01/10] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
  2021-06-08 10:25 ` [PATCH v5 01/10] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml Steven Lee
@ 2021-06-09  0:42   ` Andrew Jeffery
  2021-06-10 16:18   ` Rob Herring
  1 sibling, 0 replies; 31+ messages in thread
From: Andrew Jeffery @ 2021-06-09  0:42 UTC (permalink / raw)
  To: Steven Lee, Linus Walleij, Bartosz Golaszewski, Rob Herring,
	Joel Stanley, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: Hongwei Zhang, Ryan Chen, Billy Tsai



On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> sgpio-aspeed bindings should be converted to yaml format.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  .../bindings/gpio/aspeed,sgpio.yaml           | 75 +++++++++++++++++++
>  .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ------------
>  2 files changed, 75 insertions(+), 46 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
>  delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml 
> b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> new file mode 100644
> index 000000000000..b2ae211411ff
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> @@ -0,0 +1,75 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed SGPIO controller
> +
> +maintainers:
> +  - Andrew Jeffery <andrew@aj.id.au>
> +
> +description:
> +  This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 
> 80 full
> +  featured Serial GPIOs. Each of the Serial GPIO pins can be 
> programmed to
> +  support the following options
> +  - Support interrupt option for each input port and various interrupt
> +    sensitivity option (level-high, level-low, edge-high, edge-low)
> +  - Support reset tolerance option for each output port
> +  - Directly connected to APB bus and its shift clock is from APB bus 
> clock
> +    divided by a programmable value.
> +  - Co-work with external signal-chained TTL components 
> (74LV165/74LV595)
> +
> +properties:
> +  compatible:
> +    enum:
> +      - aspeed,ast2400-sgpio
> +      - aspeed,ast2500-sgpio
> +
> +  reg:
> +    maxItems: 1
> +
> +  gpio-controller: true
> +
> +  '#gpio-cells':
> +    const: 2
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  clocks:
> +    maxItems: 1
> +
> +  ngpios: true
> +
> +  bus-frequency: true

I'm not familiar enough with dt-schema to know that this does what we need, so deferring to Rob.

Looks good otherwise.

Andrew

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 03/10] ARM: dts: aspeed-g6: Add SGPIO node.
  2021-06-08 10:25 ` [PATCH v5 03/10] ARM: dts: aspeed-g6: Add SGPIO node Steven Lee
@ 2021-06-09  0:43   ` Andrew Jeffery
  2021-06-09  1:51     ` Steven Lee
  0 siblings, 1 reply; 31+ messages in thread
From: Andrew Jeffery @ 2021-06-09  0:43 UTC (permalink / raw)
  To: Steven Lee, Linus Walleij, Bartosz Golaszewski, Rob Herring,
	Joel Stanley, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: Hongwei Zhang, Ryan Chen, Billy Tsai



On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  arch/arm/boot/dts/aspeed-g6.dtsi | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index f96607b7b4e2..c55baaf94314 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -377,6 +377,34 @@
>  				#interrupt-cells = <2>;
>  			};
>  
> +			sgpiom0: sgpiom@1e780500 {
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				compatible = "aspeed,ast2600-sgpiom-128";
> +				reg = <0x1e780500 0x100>;
> +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&syscon ASPEED_CLK_APB2>;

The example in the binding document used ASPEED_CLK_APB. Which is correct? I assume ASPEED_CLK_APB2?

> +				interrupt-controller;
> +				bus-frequency = <12000000>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_sgpm1_default>;
> +				status = "disabled";
> +			};
> +
> +			sgpiom1: sgpiom@1e780600 {
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				compatible = "aspeed,ast2600-sgpiom-80";
> +				reg = <0x1e780600 0x100>;
> +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&syscon ASPEED_CLK_APB2>;
> +				interrupt-controller;
> +				bus-frequency = <12000000>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_sgpm2_default>;
> +				status = "disabled";
> +			};
> +
>  			gpio1: gpio@1e780800 {
>  				#gpio-cells = <2>;
>  				gpio-controller;
> -- 
> 2.17.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 04/10] ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
  2021-06-08 10:25 ` [PATCH v5 04/10] ARM: dts: aspeed-g5: Remove ngpios from sgpio node Steven Lee
@ 2021-06-09  0:45   ` Andrew Jeffery
  0 siblings, 0 replies; 31+ messages in thread
From: Andrew Jeffery @ 2021-06-09  0:45 UTC (permalink / raw)
  To: Steven Lee, Linus Walleij, Bartosz Golaszewski, Rob Herring,
	Joel Stanley, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: Hongwei Zhang, Ryan Chen, Billy Tsai



On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> Remove ngpios property from sgpio node as it should be defined in the
> platform dts.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

I guess someone will make some noise if this breaks them.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 05/10] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
  2021-06-08 10:25 ` [PATCH v5 05/10] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support Steven Lee
@ 2021-06-09  0:52   ` Andrew Jeffery
  0 siblings, 0 replies; 31+ messages in thread
From: Andrew Jeffery @ 2021-06-09  0:52 UTC (permalink / raw)
  To: Steven Lee, Linus Walleij, Bartosz Golaszewski, Rob Herring,
	Joel Stanley, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: Hongwei Zhang, Ryan Chen, Billy Tsai



On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins.
> In the current driver, the maximum number of gpio pins of SoC is hardcoded
> as 80 and the gpio pin count mask for GPIO Configuration register is
> hardcode as GENMASK(9,6). In addition, some functions use the hardcoded
> value to calculate the gpio offset.
> The patch adds ast2600 compatibles and platform data that includes the
> max number of gpio pins supported by ast2600 and gpio pin count mask for
> GPIO Configuration register.
> The patch also modifies some functions to pass aspeed_sgpio struct for
> calculating gpio offset without using the hardcoded value.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  drivers/gpio/gpio-aspeed-sgpio.c | 107 +++++++++++++++++++++----------
>  1 file changed, 73 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> index 64e54f8c30d2..ea20a0127748 100644
> --- a/drivers/gpio/gpio-aspeed-sgpio.c
> +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> @@ -34,6 +34,12 @@
>  #define ASPEED_SGPIO_PINS_MASK		GENMASK(9, 6)
>  #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
>  #define ASPEED_SGPIO_ENABLE		BIT(0)
> +#define ASPEED_SGPIO_PINS_SHIFT		6
> +
> +struct aspeed_sgpio_pdata {
> +	const u32 pin_mask;
> +	int max_ngpios;
> +};
>  
>  struct aspeed_sgpio {
>  	struct gpio_chip chip;
> @@ -41,6 +47,7 @@ struct aspeed_sgpio {
>  	spinlock_t lock;
>  	void __iomem *base;
>  	int irq;
> +	int max_ngpios;
>  	int n_sgpio;
>  };
>  
> @@ -75,7 +82,13 @@ static const struct aspeed_sgpio_bank 
> aspeed_sgpio_banks[] = {
>  		.val_regs = 0x0038,
>  		.rdata_reg = 0x0078,
>  		.irq_regs = 0x003C,
> -		.names = { "I", "J" },
> +		.names = { "I", "J", "K", "L" },
> +	},
> +	{
> +		.val_regs = 0x0090,
> +		.rdata_reg = 0x007C,
> +		.irq_regs = 0x0094,
> +		.names = { "M", "N", "O", "P" },
>  	},
>  };
>  
> @@ -121,15 +134,15 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
>  	}
>  }
>  
> -#define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
> -#define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
> -#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
> +#define GPIO_BANK(gpio, x)    (((x) % (gpio)->max_ngpios) >> 5)
> +#define GPIO_OFFSET(x)        ((x) & GENMASK(4, 0))
> +#define GPIO_BIT(gpio, x)     BIT(GPIO_OFFSET((x) % (gpio)->max_ngpios))
>  
> -static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
> +static const struct aspeed_sgpio_bank *to_bank(unsigned int offset, 
> const struct aspeed_sgpio *gpio)

Bit of a nit-pick, but again here, the context pointer (const struct aspeed_sgpio *) should be the first argument.

>  {
>  	unsigned int bank;
>  
> -	bank = GPIO_BANK(offset);
> +	bank = GPIO_BANK(gpio, offset);
>  
>  	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
>  	return &aspeed_sgpio_banks[bank];
> @@ -139,18 +152,19 @@ static int aspeed_sgpio_init_valid_mask(struct 
> gpio_chip *gc,
>  		unsigned long *valid_mask, unsigned int ngpios)
>  {
>  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
> +	int max_ngpios = sgpio->max_ngpios;
>  	int n = sgpio->n_sgpio;
> -	int c = SGPIO_OUTPUT_OFFSET - n;
> +	int c = max_ngpios - n;
>  
> -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> +	WARN_ON(ngpios < max_ngpios * 2);
>  
>  	/* input GPIOs in the lower range */
>  	bitmap_set(valid_mask, 0, n);
>  	bitmap_clear(valid_mask, n, c);
>  
> -	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
> -	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
> -	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
> +	/* output GPIOS above max_ngpios */
> +	bitmap_set(valid_mask, max_ngpios, n);
> +	bitmap_clear(valid_mask, max_ngpios + n, c);
>  
>  	return 0;
>  }
> @@ -161,30 +175,30 @@ static void 
> aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
>  	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
>  	int n = sgpio->n_sgpio;
>  
> -	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
> +	WARN_ON(ngpios < sgpio->max_ngpios * 2);
>  
>  	/* input GPIOs in the lower range */
>  	bitmap_set(valid_mask, 0, n);
>  	bitmap_clear(valid_mask, n, ngpios - n);
>  }
>  
> -static bool aspeed_sgpio_is_input(unsigned int offset)
> +static bool aspeed_sgpio_is_input(unsigned int offset, const struct 
> aspeed_sgpio *gpio)
>  {
> -	return offset < SGPIO_OUTPUT_OFFSET;
> +	return offset < gpio->max_ngpios;
>  }
>  
>  static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
>  {
>  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
>  	unsigned long flags;
>  	enum aspeed_sgpio_reg reg;
>  	int rc = 0;
>  
>  	spin_lock_irqsave(&gpio->lock, flags);
>  
> -	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
> -	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
> +	reg = aspeed_sgpio_is_input(offset, gpio) ? reg_val : reg_rdata;
> +	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(gpio, offset));
>  
>  	spin_unlock_irqrestore(&gpio->lock, flags);
>  
> @@ -194,11 +208,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, 
> unsigned int offset)
>  static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, 
> int val)
>  {
>  	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> -	const struct aspeed_sgpio_bank *bank = to_bank(offset);
> +	const struct aspeed_sgpio_bank *bank = to_bank(offset, gpio);
>  	void __iomem *addr_r, *addr_w;
>  	u32 reg = 0;
>  
> -	if (aspeed_sgpio_is_input(offset))
> +	if (aspeed_sgpio_is_input(offset, gpio))
>  		return -EINVAL;
>  
>  	/* Since this is an output, read the cached value from rdata, then
> @@ -209,9 +223,9 @@ static int sgpio_set_value(struct gpio_chip *gc, 
> unsigned int offset, int val)
>  	reg = ioread32(addr_r);
>  
>  	if (val)
> -		reg |= GPIO_BIT(offset);
> +		reg |= GPIO_BIT(gpio, offset);
>  	else
> -		reg &= ~GPIO_BIT(offset);
> +		reg &= ~GPIO_BIT(gpio, offset);
>  
>  	iowrite32(reg, addr_w);
>  
> @@ -232,7 +246,9 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, 
> unsigned int offset, int val)
>  
>  static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
>  {
> -	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
> +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> +
> +	return aspeed_sgpio_is_input(offset, gpio) ? 0 : -EINVAL;
>  }
>  
>  static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int 
> offset, int val)
> @@ -253,7 +269,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip 
> *gc, unsigned int offset, int v
>  
>  static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned 
> int offset)
>  {
> -	return !!aspeed_sgpio_is_input(offset);
> +	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
> +
> +	return !!aspeed_sgpio_is_input(offset, gpio);
>  }
>  
>  static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
> @@ -268,8 +286,8 @@ static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
>  	WARN_ON(!internal);
>  
>  	*gpio = internal;
> -	*bank = to_bank(*offset);
> -	*bit = GPIO_BIT(*offset);
> +	*bank = to_bank(*offset, internal);
> +	*bit = GPIO_BIT(internal, *offset);
>  }
>  
>  static void aspeed_sgpio_irq_ack(struct irq_data *d)
> @@ -466,9 +484,21 @@ static int aspeed_sgpio_setup_irqs(struct 
> aspeed_sgpio *gpio,
>  	return 0;
>  }
>  
> +static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> +	.max_ngpios = 128,
> +	.pin_mask = GENMASK(10, 6),
> +};
> +
> +static const struct aspeed_sgpio_pdata ast2600_sgpiom_80_pdata = {
> +	.max_ngpios = 80,
> +	.pin_mask = GENMASK(10, 6),
> +};
> +
>  static const struct of_device_id aspeed_sgpio_of_table[] = {
>  	{ .compatible = "aspeed,ast2400-sgpio" },
>  	{ .compatible = "aspeed,ast2500-sgpio" },

What happened to defining platform data for the 2400 and 2500 ...

> +	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = 
> &ast2600_sgpiom_128_pdata, },
> +	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = 
> &ast2600_sgpiom_80_pdata, },
>  	{}
>  };
>  
> @@ -476,10 +506,11 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
>  
>  static int __init aspeed_sgpio_probe(struct platform_device *pdev)
>  {
> +	u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
> +	const struct aspeed_sgpio_pdata *pdata;
>  	struct aspeed_sgpio *gpio;
> -	u32 nr_gpios, sgpio_freq, sgpio_clk_div;
> -	int rc;
>  	unsigned long apb_freq;
> +	int rc;
>  
>  	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
>  	if (!gpio)
> @@ -489,13 +520,22 @@ static int __init aspeed_sgpio_probe(struct 
> platform_device *pdev)
>  	if (IS_ERR(gpio->base))
>  		return PTR_ERR(gpio->base);
>  
> +	pdata = device_get_match_data(&pdev->dev);
> +	if (pdata) {
> +		gpio->max_ngpios = pdata->max_ngpios;
> +		pin_mask = pdata->pin_mask;
> +	} else {
> +		gpio->max_ngpios = MAX_NR_HW_SGPIO;
> +		pin_mask = ASPEED_SGPIO_PINS_MASK;
> +	}
> +

... because we should avoid introducing this branch if possible.

Aside from these two minor issues, it looks okay to me.

Andrew

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 06/10] gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data.
  2021-06-08 10:25 ` [PATCH v5 06/10] gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data Steven Lee
@ 2021-06-09  0:55   ` Andrew Jeffery
  2021-06-09  4:12     ` Steven Lee
  0 siblings, 1 reply; 31+ messages in thread
From: Andrew Jeffery @ 2021-06-09  0:55 UTC (permalink / raw)
  To: Steven Lee, Linus Walleij, Bartosz Golaszewski, Rob Herring,
	Joel Stanley, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: Hongwei Zhang, Ryan Chen, Billy Tsai



On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> We use platform data to store GPIO pin mask and the max number of
> available GPIO pins for AST2600.
> Refactor driver to also add the platform data for AST2400/AST2500 and
> remove unused MAX_NR_HW_SGPIO and ASPEED_SGPIO_PINS_MASK macros.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  drivers/gpio/gpio-aspeed-sgpio.c | 34 +++++++++++---------------------
>  1 file changed, 12 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> index ea20a0127748..7d0a4f6fd9d1 100644
> --- a/drivers/gpio/gpio-aspeed-sgpio.c
> +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> @@ -17,21 +17,8 @@
>  #include <linux/spinlock.h>
>  #include <linux/string.h>
>  
> -/*
> - * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
> - * slots within the clocked serial GPIO data). Since each HW GPIO is both an
> - * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
> - * device.
> - *
> - * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
> - * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
> - */
> -#define MAX_NR_HW_SGPIO			80
> -#define SGPIO_OUTPUT_OFFSET		MAX_NR_HW_SGPIO
> -
>  #define ASPEED_SGPIO_CTRL		0x54
>  
> -#define ASPEED_SGPIO_PINS_MASK		GENMASK(9, 6)
>  #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
>  #define ASPEED_SGPIO_ENABLE		BIT(0)
>  #define ASPEED_SGPIO_PINS_SHIFT		6
> @@ -484,6 +471,11 @@ static int aspeed_sgpio_setup_irqs(struct 
> aspeed_sgpio *gpio,
>  	return 0;
>  }
>  
> +static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
> +	.max_ngpios = 80,
> +	.pin_mask = GENMASK(9, 6),
> +};
> +
>  static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
>  	.max_ngpios = 128,
>  	.pin_mask = GENMASK(10, 6),
> @@ -495,8 +487,8 @@ static const struct aspeed_sgpio_pdata 
> ast2600_sgpiom_80_pdata = {
>  };
>  
>  static const struct of_device_id aspeed_sgpio_of_table[] = {
> -	{ .compatible = "aspeed,ast2400-sgpio" },
> -	{ .compatible = "aspeed,ast2500-sgpio" },
> +	{ .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, 
> },
> +	{ .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, 
> },
>  	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = 
> &ast2600_sgpiom_128_pdata, },
>  	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = 
> &ast2600_sgpiom_80_pdata, },
>  	{}
> @@ -521,13 +513,11 @@ static int __init aspeed_sgpio_probe(struct 
> platform_device *pdev)
>  		return PTR_ERR(gpio->base);
>  
>  	pdata = device_get_match_data(&pdev->dev);
> -	if (pdata) {
> -		gpio->max_ngpios = pdata->max_ngpios;
> -		pin_mask = pdata->pin_mask;
> -	} else {
> -		gpio->max_ngpios = MAX_NR_HW_SGPIO;
> -		pin_mask = ASPEED_SGPIO_PINS_MASK;
> -	}
> +	if (!pdata)
> +		return -EINVAL;
> +
> +	gpio->max_ngpios = pdata->max_ngpios;
> +	pin_mask = pdata->pin_mask;

Hmm, okay, maybe just re-order the patches so this commit comes before the previous one. That way we don't immediately rip out this condition that we just introduced in the previous patch.

I think I suggested squashing it into the previous patch, but with the removal of the comments and macros I think it's worth leaving it separate, just reordered.

Andrew

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 10/10] gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
  2021-06-08 10:25 ` [PATCH v5 10/10] gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8 Steven Lee
@ 2021-06-09  0:56   ` Andrew Jeffery
  0 siblings, 0 replies; 31+ messages in thread
From: Andrew Jeffery @ 2021-06-09  0:56 UTC (permalink / raw)
  To: Steven Lee, Linus Walleij, Bartosz Golaszewski, Rob Herring,
	Joel Stanley, open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: Hongwei Zhang, Ryan Chen, Billy Tsai



On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> Add an else-if condition in the probe function to check whether ngpios is
> multiple of 8.
> Per AST datasheet, numbers of available serial GPIO pins in Serial GPIO
> Configuration Register must be n bytes. For instance, if n = 1, it means
> AST SoC supports 8 GPIO pins.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 03/10] ARM: dts: aspeed-g6: Add SGPIO node.
  2021-06-09  0:43   ` Andrew Jeffery
@ 2021-06-09  1:51     ` Steven Lee
  2021-06-09  2:19       ` Andrew Jeffery
  0 siblings, 1 reply; 31+ messages in thread
From: Steven Lee @ 2021-06-09  1:51 UTC (permalink / raw)
  To: Andrew Jeffery
  Cc: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai

The 06/09/2021 08:43, Andrew Jeffery wrote:
> 
> 
> On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> > AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
> > with 80 pins.
> > 
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > ---
> >  arch/arm/boot/dts/aspeed-g6.dtsi | 28 ++++++++++++++++++++++++++++
> >  1 file changed, 28 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> > index f96607b7b4e2..c55baaf94314 100644
> > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> > @@ -377,6 +377,34 @@
> >  				#interrupt-cells = <2>;
> >  			};
> >  
> > +			sgpiom0: sgpiom@1e780500 {
> > +				#gpio-cells = <2>;
> > +				gpio-controller;
> > +				compatible = "aspeed,ast2600-sgpiom-128";
> > +				reg = <0x1e780500 0x100>;
> > +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&syscon ASPEED_CLK_APB2>;
> 
> The example in the binding document used ASPEED_CLK_APB. Which is correct? I assume ASPEED_CLK_APB2?
> 

The example in the binding document is for aspeed-g5.
aspeed-g5 and aspeed-g6 use different clocks.
Should I add a new patch for adding an example for aspeed-g6?

> > +				interrupt-controller;
> > +				bus-frequency = <12000000>;
> > +				pinctrl-names = "default";
> > +				pinctrl-0 = <&pinctrl_sgpm1_default>;
> > +				status = "disabled";
> > +			};
> > +
> > +			sgpiom1: sgpiom@1e780600 {
> > +				#gpio-cells = <2>;
> > +				gpio-controller;
> > +				compatible = "aspeed,ast2600-sgpiom-80";
> > +				reg = <0x1e780600 0x100>;
> > +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&syscon ASPEED_CLK_APB2>;
> > +				interrupt-controller;
> > +				bus-frequency = <12000000>;
> > +				pinctrl-names = "default";
> > +				pinctrl-0 = <&pinctrl_sgpm2_default>;
> > +				status = "disabled";
> > +			};
> > +
> >  			gpio1: gpio@1e780800 {
> >  				#gpio-cells = <2>;
> >  				gpio-controller;
> > -- 
> > 2.17.1
> > 
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 03/10] ARM: dts: aspeed-g6: Add SGPIO node.
  2021-06-09  1:51     ` Steven Lee
@ 2021-06-09  2:19       ` Andrew Jeffery
  0 siblings, 0 replies; 31+ messages in thread
From: Andrew Jeffery @ 2021-06-09  2:19 UTC (permalink / raw)
  To: Steven Lee
  Cc: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai



On Wed, 9 Jun 2021, at 11:21, Steven Lee wrote:
> The 06/09/2021 08:43, Andrew Jeffery wrote:
> > 
> > 
> > On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> > > AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
> > > with 80 pins.
> > > 
> > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > > ---
> > >  arch/arm/boot/dts/aspeed-g6.dtsi | 28 ++++++++++++++++++++++++++++
> > >  1 file changed, 28 insertions(+)
> > > 
> > > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> > > index f96607b7b4e2..c55baaf94314 100644
> > > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> > > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> > > @@ -377,6 +377,34 @@
> > >  				#interrupt-cells = <2>;
> > >  			};
> > >  
> > > +			sgpiom0: sgpiom@1e780500 {
> > > +				#gpio-cells = <2>;
> > > +				gpio-controller;
> > > +				compatible = "aspeed,ast2600-sgpiom-128";
> > > +				reg = <0x1e780500 0x100>;
> > > +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&syscon ASPEED_CLK_APB2>;
> > 
> > The example in the binding document used ASPEED_CLK_APB. Which is correct? I assume ASPEED_CLK_APB2?
> > 
> 
> The example in the binding document is for aspeed-g5.
> aspeed-g5 and aspeed-g6 use different clocks.
> Should I add a new patch for adding an example for aspeed-g6?
> 

Oh, I missed that. Never mind then!

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 06/10] gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data.
  2021-06-09  0:55   ` Andrew Jeffery
@ 2021-06-09  4:12     ` Steven Lee
  2021-06-09  6:45       ` Andrew Jeffery
  0 siblings, 1 reply; 31+ messages in thread
From: Steven Lee @ 2021-06-09  4:12 UTC (permalink / raw)
  To: Andrew Jeffery
  Cc: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai

The 06/09/2021 08:55, Andrew Jeffery wrote:
> 
> 
> On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> > We use platform data to store GPIO pin mask and the max number of
> > available GPIO pins for AST2600.
> > Refactor driver to also add the platform data for AST2400/AST2500 and
> > remove unused MAX_NR_HW_SGPIO and ASPEED_SGPIO_PINS_MASK macros.
> > 
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > ---
> >  drivers/gpio/gpio-aspeed-sgpio.c | 34 +++++++++++---------------------
> >  1 file changed, 12 insertions(+), 22 deletions(-)
> > 
> > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > index ea20a0127748..7d0a4f6fd9d1 100644
> > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > @@ -17,21 +17,8 @@
> >  #include <linux/spinlock.h>
> >  #include <linux/string.h>
> >  
> > -/*
> > - * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
> > - * slots within the clocked serial GPIO data). Since each HW GPIO is both an
> > - * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
> > - * device.
> > - *
> > - * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
> > - * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
> > - */
> > -#define MAX_NR_HW_SGPIO			80
> > -#define SGPIO_OUTPUT_OFFSET		MAX_NR_HW_SGPIO
> > -
> >  #define ASPEED_SGPIO_CTRL		0x54
> >  
> > -#define ASPEED_SGPIO_PINS_MASK		GENMASK(9, 6)
> >  #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
> >  #define ASPEED_SGPIO_ENABLE		BIT(0)
> >  #define ASPEED_SGPIO_PINS_SHIFT		6
> > @@ -484,6 +471,11 @@ static int aspeed_sgpio_setup_irqs(struct 
> > aspeed_sgpio *gpio,
> >  	return 0;
> >  }
> >  
> > +static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
> > +	.max_ngpios = 80,
> > +	.pin_mask = GENMASK(9, 6),
> > +};
> > +
> >  static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> >  	.max_ngpios = 128,
> >  	.pin_mask = GENMASK(10, 6),
> > @@ -495,8 +487,8 @@ static const struct aspeed_sgpio_pdata 
> > ast2600_sgpiom_80_pdata = {
> >  };
> >  
> >  static const struct of_device_id aspeed_sgpio_of_table[] = {
> > -	{ .compatible = "aspeed,ast2400-sgpio" },
> > -	{ .compatible = "aspeed,ast2500-sgpio" },
> > +	{ .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, 
> > },
> > +	{ .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, 
> > },
> >  	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = 
> > &ast2600_sgpiom_128_pdata, },
> >  	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = 
> > &ast2600_sgpiom_80_pdata, },
> >  	{}
> > @@ -521,13 +513,11 @@ static int __init aspeed_sgpio_probe(struct 
> > platform_device *pdev)
> >  		return PTR_ERR(gpio->base);
> >  
> >  	pdata = device_get_match_data(&pdev->dev);
> > -	if (pdata) {
> > -		gpio->max_ngpios = pdata->max_ngpios;
> > -		pin_mask = pdata->pin_mask;
> > -	} else {
> > -		gpio->max_ngpios = MAX_NR_HW_SGPIO;
> > -		pin_mask = ASPEED_SGPIO_PINS_MASK;
> > -	}
> > +	if (!pdata)
> > +		return -EINVAL;
> > +
> > +	gpio->max_ngpios = pdata->max_ngpios;
> > +	pin_mask = pdata->pin_mask;
> 
> Hmm, okay, maybe just re-order the patches so this commit comes before the previous one. That way we don't immediately rip out this condition that we just introduced in the previous patch.
> 
> I think I suggested squashing it into the previous patch, but with the removal of the comments and macros I think it's worth leaving it separate, just reordered.
> 

I was wondering if I can squash patch-05 and patch-06 into one patch
as this patch(patch-06) requires macros, structures, and functions that
modified in the previous patch(patch-05).

Thanks,
Steven

> Andrew

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 06/10] gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data.
  2021-06-09  4:12     ` Steven Lee
@ 2021-06-09  6:45       ` Andrew Jeffery
  2021-06-11 19:02         ` Bartosz Golaszewski
  0 siblings, 1 reply; 31+ messages in thread
From: Andrew Jeffery @ 2021-06-09  6:45 UTC (permalink / raw)
  To: Steven Lee
  Cc: Linus Walleij, Bartosz Golaszewski, Rob Herring, Joel Stanley,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai



On Wed, 9 Jun 2021, at 13:42, Steven Lee wrote:
> The 06/09/2021 08:55, Andrew Jeffery wrote:
> > 
> > 
> > On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> > > We use platform data to store GPIO pin mask and the max number of
> > > available GPIO pins for AST2600.
> > > Refactor driver to also add the platform data for AST2400/AST2500 and
> > > remove unused MAX_NR_HW_SGPIO and ASPEED_SGPIO_PINS_MASK macros.
> > > 
> > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > > ---
> > >  drivers/gpio/gpio-aspeed-sgpio.c | 34 +++++++++++---------------------
> > >  1 file changed, 12 insertions(+), 22 deletions(-)
> > > 
> > > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > > index ea20a0127748..7d0a4f6fd9d1 100644
> > > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > > @@ -17,21 +17,8 @@
> > >  #include <linux/spinlock.h>
> > >  #include <linux/string.h>
> > >  
> > > -/*
> > > - * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
> > > - * slots within the clocked serial GPIO data). Since each HW GPIO is both an
> > > - * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
> > > - * device.
> > > - *
> > > - * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
> > > - * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
> > > - */
> > > -#define MAX_NR_HW_SGPIO			80
> > > -#define SGPIO_OUTPUT_OFFSET		MAX_NR_HW_SGPIO
> > > -
> > >  #define ASPEED_SGPIO_CTRL		0x54
> > >  
> > > -#define ASPEED_SGPIO_PINS_MASK		GENMASK(9, 6)
> > >  #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
> > >  #define ASPEED_SGPIO_ENABLE		BIT(0)
> > >  #define ASPEED_SGPIO_PINS_SHIFT		6
> > > @@ -484,6 +471,11 @@ static int aspeed_sgpio_setup_irqs(struct 
> > > aspeed_sgpio *gpio,
> > >  	return 0;
> > >  }
> > >  
> > > +static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
> > > +	.max_ngpios = 80,
> > > +	.pin_mask = GENMASK(9, 6),
> > > +};
> > > +
> > >  static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> > >  	.max_ngpios = 128,
> > >  	.pin_mask = GENMASK(10, 6),
> > > @@ -495,8 +487,8 @@ static const struct aspeed_sgpio_pdata 
> > > ast2600_sgpiom_80_pdata = {
> > >  };
> > >  
> > >  static const struct of_device_id aspeed_sgpio_of_table[] = {
> > > -	{ .compatible = "aspeed,ast2400-sgpio" },
> > > -	{ .compatible = "aspeed,ast2500-sgpio" },
> > > +	{ .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, 
> > > },
> > > +	{ .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, 
> > > },
> > >  	{ .compatible = "aspeed,ast2600-sgpiom-128", .data = 
> > > &ast2600_sgpiom_128_pdata, },
> > >  	{ .compatible = "aspeed,ast2600-sgpiom-80", .data = 
> > > &ast2600_sgpiom_80_pdata, },
> > >  	{}
> > > @@ -521,13 +513,11 @@ static int __init aspeed_sgpio_probe(struct 
> > > platform_device *pdev)
> > >  		return PTR_ERR(gpio->base);
> > >  
> > >  	pdata = device_get_match_data(&pdev->dev);
> > > -	if (pdata) {
> > > -		gpio->max_ngpios = pdata->max_ngpios;
> > > -		pin_mask = pdata->pin_mask;
> > > -	} else {
> > > -		gpio->max_ngpios = MAX_NR_HW_SGPIO;
> > > -		pin_mask = ASPEED_SGPIO_PINS_MASK;
> > > -	}
> > > +	if (!pdata)
> > > +		return -EINVAL;
> > > +
> > > +	gpio->max_ngpios = pdata->max_ngpios;
> > > +	pin_mask = pdata->pin_mask;
> > 
> > Hmm, okay, maybe just re-order the patches so this commit comes before the previous one. That way we don't immediately rip out this condition that we just introduced in the previous patch.
> > 
> > I think I suggested squashing it into the previous patch, but with the removal of the comments and macros I think it's worth leaving it separate, just reordered.
> > 
> 
> I was wondering if I can squash patch-05 and patch-06 into one patch
> as this patch(patch-06) requires macros, structures, and functions that
> modified in the previous patch(patch-05).

Yeah, fair enough. Just squash them.

Cheers,

Andrew

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 00/10] ASPEED sgpio driver enhancement.
  2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
                   ` (9 preceding siblings ...)
  2021-06-08 10:25 ` [PATCH v5 10/10] gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8 Steven Lee
@ 2021-06-09 10:54 ` Linus Walleij
  2021-06-10  2:24   ` Steven Lee
  10 siblings, 1 reply; 31+ messages in thread
From: Linus Walleij @ 2021-06-09 10:54 UTC (permalink / raw)
  To: Steven Lee
  Cc: Bartosz Golaszewski, Rob Herring, Joel Stanley, Andrew Jeffery,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai

On Tue, Jun 8, 2021 at 12:26 PM Steven Lee <steven_lee@aspeedtech.com> wrote:

> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
> supports up to 80 pins.
> In the current driver design, the max number of sgpio pins is hardcoded
> in macro MAX_NR_HW_SGPIO and the value is 80.
>
> For supporting sgpio master interfaces of AST2600 SoC, the patch series
> contains the following enhancement:
> - Convert txt dt-bindings to yaml.
> - Update aspeed-g6 dtsi to support the enhanced sgpio.
> - Define max number of gpio pins in ast2600 platform data. Old chip
>   uses the original hardcoded value.
> - Support muiltiple SGPIO master interfaces.
> - Support up to 128 pins.
> - Support wdt reset tolerance.
> - Fix irq_chip issues which causes multiple sgpio devices use the same
>   irq_chip data.
> - Replace all of_*() APIs with device_*().
>
> Changes from v4:

v5 looks good to me!

I just need Rob's or another DT persons nod on the bindings (or timeout)
before I merge it. Poke me if nothing happens.

>   ARM: dts: aspeed-g6: Add SGPIO node.
>   ARM: dts: aspeed-g5: Remove ngpios from sgpio node.

These two need to be merged through the SoC tree, the rest I will handle.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 00/10] ASPEED sgpio driver enhancement.
  2021-06-09 10:54 ` [PATCH v5 00/10] ASPEED sgpio driver enhancement Linus Walleij
@ 2021-06-10  2:24   ` Steven Lee
  2021-06-10  7:50     ` Linus Walleij
  0 siblings, 1 reply; 31+ messages in thread
From: Steven Lee @ 2021-06-10  2:24 UTC (permalink / raw)
  To: Linus Walleij
  Cc: Bartosz Golaszewski, Rob Herring, Joel Stanley, Andrew Jeffery,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai

The 06/09/2021 18:54, Linus Walleij wrote:
> On Tue, Jun 8, 2021 at 12:26 PM Steven Lee <steven_lee@aspeedtech.com> wrote:
> 
> > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
> > supports up to 80 pins.
> > In the current driver design, the max number of sgpio pins is hardcoded
> > in macro MAX_NR_HW_SGPIO and the value is 80.
> >
> > For supporting sgpio master interfaces of AST2600 SoC, the patch series
> > contains the following enhancement:
> > - Convert txt dt-bindings to yaml.
> > - Update aspeed-g6 dtsi to support the enhanced sgpio.
> > - Define max number of gpio pins in ast2600 platform data. Old chip
> >   uses the original hardcoded value.
> > - Support muiltiple SGPIO master interfaces.
> > - Support up to 128 pins.
> > - Support wdt reset tolerance.
> > - Fix irq_chip issues which causes multiple sgpio devices use the same
> >   irq_chip data.
> > - Replace all of_*() APIs with device_*().
> >
> > Changes from v4:
> 
> v5 looks good to me!
> 
> I just need Rob's or another DT persons nod on the bindings (or timeout)
> before I merge it. Poke me if nothing happens.
> 
> >   ARM: dts: aspeed-g6: Add SGPIO node.
> >   ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
> 
> These two need to be merged through the SoC tree, the rest I will handle.
> 
Hi Linus, Andrew,

Per the comment in the following mail
https://lkml.org/lkml/2021/6/9/317

I was wondering if I should prepare v6 for the currnet solution or
I should drop this patch series then prepare another patch for the
new solution(piar GPIO input/output) which breaks userspace but is
better than the current solution.

Thanks,
Steven

> Yours,
> Linus Walleij

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 00/10] ASPEED sgpio driver enhancement.
  2021-06-10  2:24   ` Steven Lee
@ 2021-06-10  7:50     ` Linus Walleij
  2021-06-10  8:39       ` Steven Lee
  0 siblings, 1 reply; 31+ messages in thread
From: Linus Walleij @ 2021-06-10  7:50 UTC (permalink / raw)
  To: Steven Lee
  Cc: Bartosz Golaszewski, Rob Herring, Joel Stanley, Andrew Jeffery,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai

On Thu, Jun 10, 2021 at 4:24 AM Steven Lee <steven_lee@aspeedtech.com> wrote:

> Per the comment in the following mail
> https://lkml.org/lkml/2021/6/9/317
>
> I was wondering if I should prepare v6 for the currnet solution or
> I should drop this patch series then prepare another patch for the
> new solution(piar GPIO input/output) which breaks userspace but is
> better than the current solution.

I would say just go ahead with the new solution. AFAIK Aspeed
has pretty tight control over what kind of userspace run on these
systems.

BTW please influence Aspeed to use the GPIO character device
and ligpiod
https://git.kernel.org/pub/scm/libs/libgpiod/libgpiod.git/
if you are doing any kind of userspace GPIO control (which I
suspect that you do).

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 00/10] ASPEED sgpio driver enhancement.
  2021-06-10  7:50     ` Linus Walleij
@ 2021-06-10  8:39       ` Steven Lee
  0 siblings, 0 replies; 31+ messages in thread
From: Steven Lee @ 2021-06-10  8:39 UTC (permalink / raw)
  To: Linus Walleij
  Cc: Bartosz Golaszewski, Rob Herring, Joel Stanley, Andrew Jeffery,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai

The 06/10/2021 15:50, Linus Walleij wrote:
> On Thu, Jun 10, 2021 at 4:24 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
> 
> > Per the comment in the following mail
> > https://lkml.org/lkml/2021/6/9/317
> >
> > I was wondering if I should prepare v6 for the currnet solution or
> > I should drop this patch series then prepare another patch for the
> > new solution(piar GPIO input/output) which breaks userspace but is
> > better than the current solution.
> 
> I would say just go ahead with the new solution. AFAIK Aspeed
> has pretty tight control over what kind of userspace run on these
> systems.
> 
> BTW please influence Aspeed to use the GPIO character device
> and ligpiod
> https://git.kernel.org/pub/scm/libs/libgpiod/libgpiod.git/
> if you are doing any kind of userspace GPIO control (which I
> suspect that you do).
> 

We currently use gpioset and gpioget that provided by libgpiod to test
aspeed gpio and sgpio drivers.

For the current solution on AST2600,
the valid range of input pins  is 0 ~ 127,
the valid range of output pins is 128 ~ 255.
So we access input pins by the following command

```
gpioget $chipId 0 1 2 3 4 ... 127
```

and access output pins by the following command

```
gpioset $chipId 128=1 129=0 130=1 131=1 ... 255=1

```


The new solution will change the gpio id order as follows
Input:
```
gpioget $chipId 0 2 4 6 8 ... 254

```

Output:

```
gpioset $chipId 1=1 3=0 5=1 7=1 ... 255=1

```

Thanks,
Steven

> Yours,
> Linus Walleij

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 01/10] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
  2021-06-08 10:25 ` [PATCH v5 01/10] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml Steven Lee
  2021-06-09  0:42   ` Andrew Jeffery
@ 2021-06-10 16:18   ` Rob Herring
  1 sibling, 0 replies; 31+ messages in thread
From: Rob Herring @ 2021-06-10 16:18 UTC (permalink / raw)
  To: Steven Lee
  Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Joel Stanley, Linus Walleij, billy_tsai, Bartosz Golaszewski,
	Andrew Jeffery, moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Rob Herring, ryan_chen, Hongweiz, open list:GPIO SUBSYSTEM

On Tue, 08 Jun 2021 18:25:36 +0800, Steven Lee wrote:
> sgpio-aspeed bindings should be converted to yaml format.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  .../bindings/gpio/aspeed,sgpio.yaml           | 75 +++++++++++++++++++
>  .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ------------
>  2 files changed, 75 insertions(+), 46 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
>  delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 02/10] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.
  2021-06-08 10:25 ` [PATCH v5 02/10] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles Steven Lee
@ 2021-06-10 16:23   ` Rob Herring
  2021-06-10 23:27     ` Andrew Jeffery
  0 siblings, 1 reply; 31+ messages in thread
From: Rob Herring @ 2021-06-10 16:23 UTC (permalink / raw)
  To: Steven Lee
  Cc: Linus Walleij, Bartosz Golaszewski, Joel Stanley, Andrew Jeffery,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list, Hongweiz,
	ryan_chen, billy_tsai

On Tue, Jun 08, 2021 at 06:25:37PM +0800, Steven Lee wrote:
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins. Add ast2600-sgpiom0-80 and ast2600-sgpiom-128 compatibles
> and update descriptions to introduce the max number of available gpio
> pins that AST2600 supported.
> 
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> ---
>  Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> index b2ae211411ff..0e42eded3c1e 100644
> --- a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> +++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> @@ -10,9 +10,10 @@ maintainers:
>    - Andrew Jeffery <andrew@aj.id.au>
>  
>  description:
> -  This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
> -  featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
> -  support the following options
> +  This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
> +  AST2600 have two sgpio master one with 128 pins another one with 80 pins,
> +  AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
> +  GPIO pins can be programmed to support the following options
>    - Support interrupt option for each input port and various interrupt
>      sensitivity option (level-high, level-low, edge-high, edge-low)
>    - Support reset tolerance option for each output port
> @@ -25,6 +26,8 @@ properties:
>      enum:
>        - aspeed,ast2400-sgpio
>        - aspeed,ast2500-sgpio
> +      - aspeed,ast2600-sgpiom-80
> +      - aspeed,ast2600-sgpiom-128

If the number of GPIOs is the only difference, then I don't think you 
should get rid of ngpios. It's one thing if it varies from one SoC to 
the next, but if something is per instance we should have a property.

Rob

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 02/10] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.
  2021-06-10 16:23   ` Rob Herring
@ 2021-06-10 23:27     ` Andrew Jeffery
  2021-06-16 15:20       ` Rob Herring
  0 siblings, 1 reply; 31+ messages in thread
From: Andrew Jeffery @ 2021-06-10 23:27 UTC (permalink / raw)
  To: Rob Herring, Steven Lee
  Cc: Linus Walleij, Bartosz Golaszewski, Joel Stanley,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai



On Fri, 11 Jun 2021, at 01:53, Rob Herring wrote:
> On Tue, Jun 08, 2021 at 06:25:37PM +0800, Steven Lee wrote:
> > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > with 80 pins. Add ast2600-sgpiom0-80 and ast2600-sgpiom-128 compatibles
> > and update descriptions to introduce the max number of available gpio
> > pins that AST2600 supported.
> > 
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> >  Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 9 ++++++---
> >  1 file changed, 6 insertions(+), 3 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> > index b2ae211411ff..0e42eded3c1e 100644
> > --- a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> > +++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> > @@ -10,9 +10,10 @@ maintainers:
> >    - Andrew Jeffery <andrew@aj.id.au>
> >  
> >  description:
> > -  This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
> > -  featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
> > -  support the following options
> > +  This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
> > +  AST2600 have two sgpio master one with 128 pins another one with 80 pins,
> > +  AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
> > +  GPIO pins can be programmed to support the following options
> >    - Support interrupt option for each input port and various interrupt
> >      sensitivity option (level-high, level-low, edge-high, edge-low)
> >    - Support reset tolerance option for each output port
> > @@ -25,6 +26,8 @@ properties:
> >      enum:
> >        - aspeed,ast2400-sgpio
> >        - aspeed,ast2500-sgpio
> > +      - aspeed,ast2600-sgpiom-80
> > +      - aspeed,ast2600-sgpiom-128
> 
> If the number of GPIOs is the only difference, then I don't think you 
> should get rid of ngpios. It's one thing if it varies from one SoC to 
> the next, but if something is per instance we should have a property.
> 

There are two issues:

1. The maximum number of GPIOs supported by the controller
2. The maximum number of GPIOs supported by the platform

These are different because of what the controller does - here's some previous discussion on the topic:

https://lore.kernel.org/linux-gpio/f2875111-9ba9-43b7-b2a4-d00c8725f5a0@www.fastmail.com/

We've used ngpios to describe 2; this decision was made prior to the 2600 design - the SGPIO controller for both the 2400 and 2500 supported a maximum of 80 GPIOs. With the 2600 we have to differentiate between the two SGPIO controllers because they support a different maximum number of GPIOs. The proposed approach of different compatibles keeps the behaviour of ngpios the same across all controller implementations.

Cheers,

Andrew

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 06/10] gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data.
  2021-06-09  6:45       ` Andrew Jeffery
@ 2021-06-11 19:02         ` Bartosz Golaszewski
  2021-06-15  4:22           ` Steven Lee
  0 siblings, 1 reply; 31+ messages in thread
From: Bartosz Golaszewski @ 2021-06-11 19:02 UTC (permalink / raw)
  To: Steven Lee
  Cc: Linus Walleij, Rob Herring, Joel Stanley,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Andrew Jeffery, Billy Tsai

On Wed, Jun 9, 2021 at 8:46 AM Andrew Jeffery <andrew@aj.id.au> wrote:
>
>
>
> On Wed, 9 Jun 2021, at 13:42, Steven Lee wrote:
> > The 06/09/2021 08:55, Andrew Jeffery wrote:
> > >
> > >
> > > On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> > > > We use platform data to store GPIO pin mask and the max number of
> > > > available GPIO pins for AST2600.
> > > > Refactor driver to also add the platform data for AST2400/AST2500 and
> > > > remove unused MAX_NR_HW_SGPIO and ASPEED_SGPIO_PINS_MASK macros.
> > > >
> > > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > > > ---
> > > >  drivers/gpio/gpio-aspeed-sgpio.c | 34 +++++++++++---------------------
> > > >  1 file changed, 12 insertions(+), 22 deletions(-)
> > > >
> > > > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > > > index ea20a0127748..7d0a4f6fd9d1 100644
> > > > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > > > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > > > @@ -17,21 +17,8 @@
> > > >  #include <linux/spinlock.h>
> > > >  #include <linux/string.h>
> > > >
> > > > -/*
> > > > - * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
> > > > - * slots within the clocked serial GPIO data). Since each HW GPIO is both an
> > > > - * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
> > > > - * device.
> > > > - *
> > > > - * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
> > > > - * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
> > > > - */
> > > > -#define MAX_NR_HW_SGPIO                  80
> > > > -#define SGPIO_OUTPUT_OFFSET              MAX_NR_HW_SGPIO
> > > > -
> > > >  #define ASPEED_SGPIO_CTRL                0x54
> > > >
> > > > -#define ASPEED_SGPIO_PINS_MASK           GENMASK(9, 6)
> > > >  #define ASPEED_SGPIO_CLK_DIV_MASK        GENMASK(31, 16)
> > > >  #define ASPEED_SGPIO_ENABLE              BIT(0)
> > > >  #define ASPEED_SGPIO_PINS_SHIFT          6
> > > > @@ -484,6 +471,11 @@ static int aspeed_sgpio_setup_irqs(struct
> > > > aspeed_sgpio *gpio,
> > > >   return 0;
> > > >  }
> > > >
> > > > +static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
> > > > + .max_ngpios = 80,
> > > > + .pin_mask = GENMASK(9, 6),
> > > > +};
> > > > +
> > > >  static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> > > >   .max_ngpios = 128,
> > > >   .pin_mask = GENMASK(10, 6),
> > > > @@ -495,8 +487,8 @@ static const struct aspeed_sgpio_pdata
> > > > ast2600_sgpiom_80_pdata = {
> > > >  };
> > > >
> > > >  static const struct of_device_id aspeed_sgpio_of_table[] = {
> > > > - { .compatible = "aspeed,ast2400-sgpio" },
> > > > - { .compatible = "aspeed,ast2500-sgpio" },
> > > > + { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata,
> > > > },
> > > > + { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata,
> > > > },
> > > >   { .compatible = "aspeed,ast2600-sgpiom-128", .data =
> > > > &ast2600_sgpiom_128_pdata, },
> > > >   { .compatible = "aspeed,ast2600-sgpiom-80", .data =
> > > > &ast2600_sgpiom_80_pdata, },
> > > >   {}
> > > > @@ -521,13 +513,11 @@ static int __init aspeed_sgpio_probe(struct
> > > > platform_device *pdev)
> > > >           return PTR_ERR(gpio->base);
> > > >
> > > >   pdata = device_get_match_data(&pdev->dev);
> > > > - if (pdata) {
> > > > -         gpio->max_ngpios = pdata->max_ngpios;
> > > > -         pin_mask = pdata->pin_mask;
> > > > - } else {
> > > > -         gpio->max_ngpios = MAX_NR_HW_SGPIO;
> > > > -         pin_mask = ASPEED_SGPIO_PINS_MASK;
> > > > - }
> > > > + if (!pdata)
> > > > +         return -EINVAL;
> > > > +
> > > > + gpio->max_ngpios = pdata->max_ngpios;
> > > > + pin_mask = pdata->pin_mask;
> > >
> > > Hmm, okay, maybe just re-order the patches so this commit comes before the previous one. That way we don't immediately rip out this condition that we just introduced in the previous patch.
> > >
> > > I think I suggested squashing it into the previous patch, but with the removal of the comments and macros I think it's worth leaving it separate, just reordered.
> > >
> >
> > I was wondering if I can squash patch-05 and patch-06 into one patch
> > as this patch(patch-06) requires macros, structures, and functions that
> > modified in the previous patch(patch-05).
>
> Yeah, fair enough. Just squash them.
>
> Cheers,
>
> Andrew

I'm ready to pick this up as soon as you respin the series.

Bart

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 06/10] gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data.
  2021-06-11 19:02         ` Bartosz Golaszewski
@ 2021-06-15  4:22           ` Steven Lee
  0 siblings, 0 replies; 31+ messages in thread
From: Steven Lee @ 2021-06-15  4:22 UTC (permalink / raw)
  To: Bartosz Golaszewski
  Cc: Linus Walleij, Rob Herring, Joel Stanley,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Andrew Jeffery, Billy Tsai

The 06/12/2021 03:02, Bartosz Golaszewski wrote:
> On Wed, Jun 9, 2021 at 8:46 AM Andrew Jeffery <andrew@aj.id.au> wrote:
> >
> >
> >
> > On Wed, 9 Jun 2021, at 13:42, Steven Lee wrote:
> > > The 06/09/2021 08:55, Andrew Jeffery wrote:
> > > >
> > > >
> > > > On Tue, 8 Jun 2021, at 19:55, Steven Lee wrote:
> > > > > We use platform data to store GPIO pin mask and the max number of
> > > > > available GPIO pins for AST2600.
> > > > > Refactor driver to also add the platform data for AST2400/AST2500 and
> > > > > remove unused MAX_NR_HW_SGPIO and ASPEED_SGPIO_PINS_MASK macros.
> > > > >
> > > > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > > > > ---
> > > > >  drivers/gpio/gpio-aspeed-sgpio.c | 34 +++++++++++---------------------
> > > > >  1 file changed, 12 insertions(+), 22 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> > > > > index ea20a0127748..7d0a4f6fd9d1 100644
> > > > > --- a/drivers/gpio/gpio-aspeed-sgpio.c
> > > > > +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> > > > > @@ -17,21 +17,8 @@
> > > > >  #include <linux/spinlock.h>
> > > > >  #include <linux/string.h>
> > > > >
> > > > > -/*
> > > > > - * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
> > > > > - * slots within the clocked serial GPIO data). Since each HW GPIO is both an
> > > > > - * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
> > > > > - * device.
> > > > > - *
> > > > > - * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
> > > > > - * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
> > > > > - */
> > > > > -#define MAX_NR_HW_SGPIO                  80
> > > > > -#define SGPIO_OUTPUT_OFFSET              MAX_NR_HW_SGPIO
> > > > > -
> > > > >  #define ASPEED_SGPIO_CTRL                0x54
> > > > >
> > > > > -#define ASPEED_SGPIO_PINS_MASK           GENMASK(9, 6)
> > > > >  #define ASPEED_SGPIO_CLK_DIV_MASK        GENMASK(31, 16)
> > > > >  #define ASPEED_SGPIO_ENABLE              BIT(0)
> > > > >  #define ASPEED_SGPIO_PINS_SHIFT          6
> > > > > @@ -484,6 +471,11 @@ static int aspeed_sgpio_setup_irqs(struct
> > > > > aspeed_sgpio *gpio,
> > > > >   return 0;
> > > > >  }
> > > > >
> > > > > +static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
> > > > > + .max_ngpios = 80,
> > > > > + .pin_mask = GENMASK(9, 6),
> > > > > +};
> > > > > +
> > > > >  static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
> > > > >   .max_ngpios = 128,
> > > > >   .pin_mask = GENMASK(10, 6),
> > > > > @@ -495,8 +487,8 @@ static const struct aspeed_sgpio_pdata
> > > > > ast2600_sgpiom_80_pdata = {
> > > > >  };
> > > > >
> > > > >  static const struct of_device_id aspeed_sgpio_of_table[] = {
> > > > > - { .compatible = "aspeed,ast2400-sgpio" },
> > > > > - { .compatible = "aspeed,ast2500-sgpio" },
> > > > > + { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata,
> > > > > },
> > > > > + { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata,
> > > > > },
> > > > >   { .compatible = "aspeed,ast2600-sgpiom-128", .data =
> > > > > &ast2600_sgpiom_128_pdata, },
> > > > >   { .compatible = "aspeed,ast2600-sgpiom-80", .data =
> > > > > &ast2600_sgpiom_80_pdata, },
> > > > >   {}
> > > > > @@ -521,13 +513,11 @@ static int __init aspeed_sgpio_probe(struct
> > > > > platform_device *pdev)
> > > > >           return PTR_ERR(gpio->base);
> > > > >
> > > > >   pdata = device_get_match_data(&pdev->dev);
> > > > > - if (pdata) {
> > > > > -         gpio->max_ngpios = pdata->max_ngpios;
> > > > > -         pin_mask = pdata->pin_mask;
> > > > > - } else {
> > > > > -         gpio->max_ngpios = MAX_NR_HW_SGPIO;
> > > > > -         pin_mask = ASPEED_SGPIO_PINS_MASK;
> > > > > - }
> > > > > + if (!pdata)
> > > > > +         return -EINVAL;
> > > > > +
> > > > > + gpio->max_ngpios = pdata->max_ngpios;
> > > > > + pin_mask = pdata->pin_mask;
> > > >
> > > > Hmm, okay, maybe just re-order the patches so this commit comes before the previous one. That way we don't immediately rip out this condition that we just introduced in the previous patch.
> > > >
> > > > I think I suggested squashing it into the previous patch, but with the removal of the comments and macros I think it's worth leaving it separate, just reordered.
> > > >
> > >
> > > I was wondering if I can squash patch-05 and patch-06 into one patch
> > > as this patch(patch-06) requires macros, structures, and functions that
> > > modified in the previous patch(patch-05).
> >
> > Yeah, fair enough. Just squash them.
> >
> > Cheers,
> >
> > Andrew
> 
> I'm ready to pick this up as soon as you respin the series.
> 

Hi Bart,

Per the discussion in the following mail threads, I may redesign
aspeed sgpio driver for the new solution.

https://lkml.org/lkml/2021/6/3/1507
https://lkml.org/lkml/2021/6/10/240

Patch02- Patch06 of this patch series will need to be modified for
the new solution, although some of them have Reviewed-by tag.

Thanks,
Steven

> Bart

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v5 02/10] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles.
  2021-06-10 23:27     ` Andrew Jeffery
@ 2021-06-16 15:20       ` Rob Herring
  0 siblings, 0 replies; 31+ messages in thread
From: Rob Herring @ 2021-06-16 15:20 UTC (permalink / raw)
  To: Andrew Jeffery
  Cc: Steven Lee, Linus Walleij, Bartosz Golaszewski, Joel Stanley,
	open list:GPIO SUBSYSTEM,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai

On Thu, Jun 10, 2021 at 5:27 PM Andrew Jeffery <andrew@aj.id.au> wrote:
>
>
>
> On Fri, 11 Jun 2021, at 01:53, Rob Herring wrote:
> > On Tue, Jun 08, 2021 at 06:25:37PM +0800, Steven Lee wrote:
> > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > > with 80 pins. Add ast2600-sgpiom0-80 and ast2600-sgpiom-128 compatibles
> > > and update descriptions to introduce the max number of available gpio
> > > pins that AST2600 supported.
> > >
> > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > > Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> > > ---
> > >  Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 9 ++++++---
> > >  1 file changed, 6 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> > > index b2ae211411ff..0e42eded3c1e 100644
> > > --- a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> > > +++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> > > @@ -10,9 +10,10 @@ maintainers:
> > >    - Andrew Jeffery <andrew@aj.id.au>
> > >
> > >  description:
> > > -  This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
> > > -  featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
> > > -  support the following options
> > > +  This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
> > > +  AST2600 have two sgpio master one with 128 pins another one with 80 pins,
> > > +  AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
> > > +  GPIO pins can be programmed to support the following options
> > >    - Support interrupt option for each input port and various interrupt
> > >      sensitivity option (level-high, level-low, edge-high, edge-low)
> > >    - Support reset tolerance option for each output port
> > > @@ -25,6 +26,8 @@ properties:
> > >      enum:
> > >        - aspeed,ast2400-sgpio
> > >        - aspeed,ast2500-sgpio
> > > +      - aspeed,ast2600-sgpiom-80
> > > +      - aspeed,ast2600-sgpiom-128
> >
> > If the number of GPIOs is the only difference, then I don't think you
> > should get rid of ngpios. It's one thing if it varies from one SoC to
> > the next, but if something is per instance we should have a property.
> >
>
> There are two issues:
>
> 1. The maximum number of GPIOs supported by the controller
> 2. The maximum number of GPIOs supported by the platform
>
> These are different because of what the controller does - here's some previous discussion on the topic:
>
> https://lore.kernel.org/linux-gpio/f2875111-9ba9-43b7-b2a4-d00c8725f5a0@www.fastmail.com/
>
> We've used ngpios to describe 2; this decision was made prior to the 2600 design - the SGPIO controller for both the 2400 and 2500 supported a maximum of 80 GPIOs. With the 2600 we have to differentiate between the two SGPIO controllers because they support a different maximum number of GPIOs. The proposed approach of different compatibles keeps the behaviour of ngpios the same across all controller implementations.

Okay, that makes sense.

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 31+ messages in thread

end of thread, other threads:[~2021-06-16 15:21 UTC | newest]

Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-08 10:25 [PATCH v5 00/10] ASPEED sgpio driver enhancement Steven Lee
2021-06-08 10:25 ` [PATCH v5 01/10] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml Steven Lee
2021-06-09  0:42   ` Andrew Jeffery
2021-06-10 16:18   ` Rob Herring
2021-06-08 10:25 ` [PATCH v5 02/10] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles Steven Lee
2021-06-10 16:23   ` Rob Herring
2021-06-10 23:27     ` Andrew Jeffery
2021-06-16 15:20       ` Rob Herring
2021-06-08 10:25 ` [PATCH v5 03/10] ARM: dts: aspeed-g6: Add SGPIO node Steven Lee
2021-06-09  0:43   ` Andrew Jeffery
2021-06-09  1:51     ` Steven Lee
2021-06-09  2:19       ` Andrew Jeffery
2021-06-08 10:25 ` [PATCH v5 04/10] ARM: dts: aspeed-g5: Remove ngpios from sgpio node Steven Lee
2021-06-09  0:45   ` Andrew Jeffery
2021-06-08 10:25 ` [PATCH v5 05/10] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support Steven Lee
2021-06-09  0:52   ` Andrew Jeffery
2021-06-08 10:25 ` [PATCH v5 06/10] gpio: gpio-aspeed-sgpio: Add AST2400 and AST2500 platform data Steven Lee
2021-06-09  0:55   ` Andrew Jeffery
2021-06-09  4:12     ` Steven Lee
2021-06-09  6:45       ` Andrew Jeffery
2021-06-11 19:02         ` Bartosz Golaszewski
2021-06-15  4:22           ` Steven Lee
2021-06-08 10:25 ` [PATCH v5 07/10] gpio: gpio-aspeed-sgpio: Add set_config function Steven Lee
2021-06-08 10:25 ` [PATCH v5 08/10] gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct Steven Lee
2021-06-08 10:25 ` [PATCH v5 09/10] gpio: gpio-aspeed-sgpio: Use generic device property APIs Steven Lee
2021-06-08 10:25 ` [PATCH v5 10/10] gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8 Steven Lee
2021-06-09  0:56   ` Andrew Jeffery
2021-06-09 10:54 ` [PATCH v5 00/10] ASPEED sgpio driver enhancement Linus Walleij
2021-06-10  2:24   ` Steven Lee
2021-06-10  7:50     ` Linus Walleij
2021-06-10  8:39       ` Steven Lee

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