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From: Jonathan Marek <jonathan@marek.ca>
To: Stephen Boyd <sboyd@kernel.org>, linux-arm-msm@vger.kernel.org
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250
Date: Sun, 27 Sep 2020 15:11:25 -0400	[thread overview]
Message-ID: <6fbd25e8-a941-5055-7141-40f7a0608d5c@marek.ca> (raw)
In-Reply-To: <160092820545.310579.6383587246524246608@swboyd.mtv.corp.google.com>

On 9/24/20 2:16 AM, Stephen Boyd wrote:
> Quoting Jonathan Marek (2020-09-23 09:10:04)
>> On 9/22/20 3:00 PM, Stephen Boyd wrote:
>>> Quoting Jonathan Marek (2020-09-11 08:34:07)
>>>> diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
>>>> new file mode 100644
>>>> index 000000000000..7c0f384a3a42
>>>> --- /dev/null
>>>> +++ b/drivers/clk/qcom/dispcc-sm8250.c
>>>> @@ -0,0 +1,1100 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
>>>> + */
>>>> +
>>> [...]
>>>> +
>>>> +static const struct clk_parent_data disp_cc_parent_data_6[] = {
>>>> +       { .fw_name = "bi_tcxo" },
>>>> +       { .fw_name = "dsi0_phy_pll_out_dsiclk" },
>>>> +       { .fw_name = "dsi1_phy_pll_out_dsiclk" },
>>>
>>> Can we remove clk postfix on these clk names?
>>>
>>
>> This is consistent with the names used in both sdm845 and sc7180
>> drivers. If this should change then those should be changed too?
> 
> If DT isn't using it already then it sounds OK to change the other
> SoCs. Otherwise fix it just for this one.
> 

Both sdm845 and sc7180 DT are using these names. I kept these names in 
the V4 I just sent, keeping things consistent is a lot more beneficial 
than dropping 3 extra characters from the DT names.

The sc7180 dispcc driver is recent and has all of these:

- dp_phy_pll_link_clk
- dp_phy_pll_vco_div_clk
- dsi0_phy_pll_out_byteclk
- dsi0_phy_pll_out_dsiclk

So I just can't imagine dropping the clk postfix is actually important.


      reply	other threads:[~2020-09-27 19:12 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-11 15:34 [PATCH v3 0/7] SM8150 and SM8250 dispcc drivers Jonathan Marek
2020-09-11 15:34 ` [PATCH v3 1/7] dt-bindings: clock: sdm845-dispcc: same name for dp_phy clocks as sc7180 Jonathan Marek
2020-09-22 22:57   ` Rob Herring
2020-09-11 15:34 ` [PATCH v3 2/7] arm64: dts: qcom: " Jonathan Marek
2020-09-11 15:34 ` [PATCH v3 3/7] dt-bindings: clock: combine qcom,sdm845-dispcc and qcom,sc7180-dispcc Jonathan Marek
2020-09-22 19:02   ` Stephen Boyd
2020-09-11 15:34 ` [PATCH v3 4/7] dt-bindings: clock: Introduce QCOM SM8150 display clock bindings Jonathan Marek
2020-09-11 15:34 ` [PATCH v3 5/7] dt-bindings: clock: Introduce QCOM SM8250 " Jonathan Marek
2020-09-22 19:04   ` Stephen Boyd
2020-09-11 15:34 ` [PATCH v3 6/7] clk: qcom: Add display clock controller driver for SM8150 Jonathan Marek
2020-09-22 19:04   ` Stephen Boyd
2020-09-23 16:24     ` Jonathan Marek
2020-09-24  6:15       ` Stephen Boyd
2020-09-11 15:34 ` [PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250 Jonathan Marek
2020-09-22 19:00   ` Stephen Boyd
2020-09-23 16:10     ` Jonathan Marek
2020-09-24  6:16       ` Stephen Boyd
2020-09-27 19:11         ` Jonathan Marek [this message]

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