From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93B8EC282C0 for ; Fri, 25 Jan 2019 12:06:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 63910218D9 for ; Fri, 25 Jan 2019 12:06:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="m4Ye+8NM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728289AbfAYMGy (ORCPT ); Fri, 25 Jan 2019 07:06:54 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:9446 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726026AbfAYMGv (ORCPT ); Fri, 25 Jan 2019 07:06:51 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 25 Jan 2019 04:06:25 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 25 Jan 2019 04:06:50 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 25 Jan 2019 04:06:50 -0800 Received: from [10.21.132.148] (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 25 Jan 2019 12:06:48 +0000 Subject: Re: [PATCH 1/6] dt-bindings: timer: add Tegra210 timer From: Jon Hunter To: Joseph Lo , Thierry Reding CC: , Daniel Lezcano , , , Thomas Gleixner , References: <20190107032810.13522-1-josephl@nvidia.com> <20190107032810.13522-2-josephl@nvidia.com> <285bd3f7-e1c0-0767-6381-4b1d748bd6db@nvidia.com> <381f94c0-6c19-0f5b-df06-91353455a4c0@nvidia.com> Message-ID: <709e24fa-02e1-96ea-2b20-acf150caff00@nvidia.com> Date: Fri, 25 Jan 2019 12:06:47 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <381f94c0-6c19-0f5b-df06-91353455a4c0@nvidia.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548417985; bh=52DdgeQgGbRQd70/mlPU5RXi/79u+o+2v3jVDcM9BgY=; h=X-PGP-Universal:Subject:From:To:CC:References:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=m4Ye+8NMkqSLhS5/KxFM7SBEYqyiWBqAZb+3coUEbF8JAsV6SakU6K4Q1V00I60xM 0BNaWEjLfKf25MLfX23QhREbXFWLRF3DgHNCR1MNNnGo4A4zj4vr6BdqJ8LtaUHqbX E91NNE/ILifqJY9XtLj4Ekx5PC2j2oYYgXlBoOkG3OoEhI/NS+UeTljtn+IzAFnEI2 HRUxhpIOQlyWlS0mnFobhs94e87kilRsp9AKFxzKA2AA6oylIVwwPLLpeLwazIxa/Q WqgY7QKQOuhNtR6bnlCGYPkGfxP3OHHCBCDGpXLrWmS4/w3Gr0YsRYyWmCnvirrJgD Kseuf97osfG9Q== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/01/2019 12:01, Jon Hunter wrote: >=20 > On 25/01/2019 03:23, Joseph Lo wrote: >> Hi Jon, >> >> Thanks for reviewing. >> >> On 1/24/19 6:30 PM, Jon Hunter wrote: >>> >>> On 07/01/2019 03:28, Joseph Lo wrote: >>>> The Tegra210 timer provides fourteen 29-bit timer counters and one >>>> 32-bit >>>> timestamp counter. The TMRs run at either a fixed 1 MHz clock rate >>>> derived >>>> from the oscillator clock (TMR0-TMR9) or directly at the oscillator >>>> clock >>>> (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodi= c, >>>> or watchdog interrupts. >>>> >>>> Cc: Daniel Lezcano >>>> Cc: Thomas Gleixner >>>> Cc: linux-kernel@vger.kernel.org >>>> Cc: devicetree@vger.kernel.org >>>> Signed-off-by: Joseph Lo >>>> --- >>>> =C2=A0 .../bindings/timer/nvidia,tegra210-timer.txt=C2=A0 | 25 +++++++= ++++++++++++ >>>> =C2=A0 1 file changed, 25 insertions(+) >>>> =C2=A0 create mode 100644 >>>> Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt >>>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt >>>> b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt >>>> new file mode 100644 >>>> index 000000000000..ba511220a669 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.tx= t >>>> @@ -0,0 +1,25 @@ >>>> +NVIDIA Tegra210 timer >>>> + >>>> +The Tegra210 timer provides fourteen 29-bit timer counters and one >>>> 32-bit >>>> +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate >>>> derived >>>> +from the oscillator clock (TMR0-TMR9) or directly at the oscillator >>>> clock >>>> +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, >>>> periodic, >>>> +or watchdog interrupts. >>>> + >>>> +Required properties: >>>> +- compatible : "nvidia,tegra210-timer". >>>> +- reg : Specifies base physical address and size of the registers. >>>> +- interrupts : A list of 4 interrupts; one per each of TMR10 through >>>> TMR13. >>> >>> Why do we only add the interrupts for TMR10 - TMR13? What about the >>> others? >>> >> >> The others (TMR0-TMR9) are occupied for other usages. TMR5 is occupied >> for the watchdog timer in the upstream kernel. And others (still in >> TMR0-TMR9) are occupied for different usages in our downstream kernel. >=20 > Where is TMR5 reserved for the watchdog? I don't see this? I see it now, it is hard-coded in the driver. I was looking at arm64 to see where it is used. Cheers Jon --=20 nvpublic