From: Xiaoyao Li <xiaoyao.li@intel.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] KVM: x86: Fix the initial value of mcg_cap
Date: Mon, 24 Oct 2022 09:37:59 +0800 [thread overview]
Message-ID: <70ea1214-38aa-3b51-9c1d-6661b3b45144@intel.com> (raw)
In-Reply-To: <Y1LmWAyG7S4bgzBs@google.com>
On 10/22/2022 2:35 AM, Sean Christopherson wrote:
> On Fri, Oct 21, 2022, Xiaoyao Li wrote:
>> On 10/21/2022 12:32 AM, Sean Christopherson wrote:
>>> If we really want to clean up this code, I think the correct approach would be to
>>> inject #GP on all relevant MSRs if CPUID.MCA==0, e.g.
>>
>> It's what I thought of as well. But I didn't find any statement in SDM of
>> "Accessing Machine Check MSRs gets #GP if no CPUID.MCA"
>
> Ugh, stupid SDM. Really old SDMs, e.g. circa 1997, explicity state in the
> CPUID.MCA entry that:
>
> Processor supports the MCG_CAP MSR.
>
> But, when Intel introduced the "Architectural MSRs" section (2001 or so), the
> wording was changed to be less explicit:
>
> The Machine Check Architecture, which provides a compatible mechanism for error
> reporting in P6 family, Pentium 4, and Intel Xeon processors, and future processors,
> is supported. The MCG_CAP MSR contains feature bits describing how many banks of
> error reporting MSRs are supported.
>
> and the entry in the MSR index just lists P6 as the dependency:
>
> IA32_MCG_CAP (MCG_CAP) Global Machine Check Capability (R/O) 06_01H
>
> So I think it's technically true that MCG_CAP is supposed to exist iff CPUID.MCA=1,
> but we'd probably need an SDM change to really be able to enforce that :-(
I'll talk to Intel architects for this. :)
next prev parent reply other threads:[~2022-10-24 1:38 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 3:16 [PATCH] KVM: x86: Fix the initial value of mcg_cap Xiaoyao Li
2022-10-20 14:27 ` Sean Christopherson
2022-10-20 15:07 ` Xiaoyao Li
2022-10-20 16:32 ` Sean Christopherson
2022-10-21 3:12 ` Xiaoyao Li
2022-10-21 18:35 ` Sean Christopherson
2022-10-24 1:37 ` Xiaoyao Li [this message]
2022-10-25 16:22 ` Tony Luck
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=70ea1214-38aa-3b51-9c1d-6661b3b45144@intel.com \
--to=xiaoyao.li@intel.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=seanjc@google.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).