From: Yunsheng Lin <linyunsheng@huawei.com>
To: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: <davem@davemloft.net>, <kuba@kernel.org>, <hawk@kernel.org>,
<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<hkallweit1@gmail.com>
Subject: Re: [PATCH net-next v2 2/2] page_pool: optimize the cpu sync operation when DMA mapping
Date: Tue, 24 Aug 2021 15:00:54 +0800 [thread overview]
Message-ID: <710fcc40-64d0-cafc-5dde-8762cc0ae457@huawei.com> (raw)
In-Reply-To: <YSOXwdLgeY1ti8ZO@enceladus>
On 2021/8/23 20:42, Ilias Apalodimas wrote:
> On Mon, Aug 23, 2021 at 11:56:48AM +0800, Yunsheng Lin wrote:
>> On 2021/8/20 17:39, Ilias Apalodimas wrote:
>>> On Fri, Aug 20, 2021 at 02:56:51PM +0800, Yunsheng Lin wrote:
[..]
>>
>> https://elixir.bootlin.com/linux/latest/source/kernel/dma/direct.h#L104
>>
>> The one thing I am not sure about is that the pool->p.offset
>> and pool->p.max_len are used to decide the sync range before this
>> patch, while the sync range is the same as the map range when doing
>> the sync in dma_map_page_attrs().
>
> I am not sure I am following here. We always sync the entire range as well
> in the current code as the mapping function is called with max_len.
>
>>
>> I assumed the above is not a issue? only sync more than we need?
>> and it won't hurt the performance?
>
> We can sync more than we need, but if it's a non-coherent architecture,
> there's a performance penalty.
Since I do not have any performance data to prove if there is a
performance penalty for non-coherent architecture, I will drop it:)
>
> Regards
> /Ilias
>>
next prev parent reply other threads:[~2021-08-24 7:01 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 6:56 [PATCH net-next v2 0/2] Some minor optimization for page pool Yunsheng Lin
2021-08-20 6:56 ` [PATCH net-next v2 1/2] page_pool: use relaxed atomic for release side accounting Yunsheng Lin
2021-08-20 7:12 ` Jesper Dangaard Brouer
2021-08-20 6:56 ` [PATCH net-next v2 2/2] page_pool: optimize the cpu sync operation when DMA mapping Yunsheng Lin
2021-08-20 9:39 ` Ilias Apalodimas
2021-08-23 3:56 ` Yunsheng Lin
2021-08-23 12:42 ` Ilias Apalodimas
2021-08-24 7:00 ` Yunsheng Lin [this message]
2021-08-24 9:04 ` Ilias Apalodimas
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