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[73.185.129.58]) by smtp.googlemail.com with ESMTPSA id m5sm6184543qkd.36.2022.02.22.06.08.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Feb 2022 06:08:59 -0800 (PST) Message-ID: <72118049-0ae0-69a9-97de-2c132e5f3b6c@linaro.org> Date: Tue, 22 Feb 2022 08:08:57 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v3 15/25] bus: mhi: ep: Add support for processing MHI endpoint interrupts Content-Language: en-US To: Manivannan Sadhasivam Cc: mhi@lists.linux.dev, quic_hemantk@quicinc.com, quic_bbhatt@quicinc.com, quic_jhugo@quicinc.com, vinod.koul@linaro.org, bjorn.andersson@linaro.org, dmitry.baryshkov@linaro.org, quic_vbadigan@quicinc.com, quic_cang@quicinc.com, quic_skananth@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220212182117.49438-1-manivannan.sadhasivam@linaro.org> <20220212182117.49438-16-manivannan.sadhasivam@linaro.org> <20220222081859.GC5029@thinkpad> From: Alex Elder In-Reply-To: <20220222081859.GC5029@thinkpad> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/22/22 2:18 AM, Manivannan Sadhasivam wrote: > On Tue, Feb 15, 2022 at 04:39:30PM -0600, Alex Elder wrote: >> On 2/12/22 12:21 PM, Manivannan Sadhasivam wrote: >>> Add support for processing MHI endpoint interrupts such as control >>> interrupt, command interrupt and channel interrupt from the host. >>> >>> The interrupts will be generated in the endpoint device whenever host >>> writes to the corresponding doorbell registers. The doorbell logic >>> is handled inside the hardware internally. >>> >>> Signed-off-by: Manivannan Sadhasivam >> >> Unless I'm mistaken, you have some bugs here. >> >> Beyond that, I question whether you should be using workqueues >> for handling all interrupts. For now, it's fine, but there >> might be room for improvement after this is accepted upstream >> (using threaded interrupt handlers, for example). >> > > Only reason I didn't use bottom halves is that the memory for TRE buffers need > to be allocated each time, so essentially the caller should not sleep. Threaded interrupt handlers can sleep. If scheduled, they run immediately after hard interrupt handlers. For receive buffers, yes, replacing a receive buffer just consumed would require an allocation, but for transmit I think it might be possible to avoid the need to do a memory allocation. (Things to think about at some future date.) > This is currently a limitation of iATU where there are only 8 windows for > mapping the host memory and each memory region size is also limited. Those are hard limitations, and probably what constrains you the most. -Alex > >> -Alex >> >>> --- >>> drivers/bus/mhi/ep/main.c | 113 +++++++++++++++++++++++++++++++++++++- >>> include/linux/mhi_ep.h | 2 + >>> 2 files changed, 113 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c >>> index ccb3c2795041..072b872e735b 100644 >>> --- a/drivers/bus/mhi/ep/main.c >>> +++ b/drivers/bus/mhi/ep/main.c >>> @@ -185,6 +185,56 @@ static void mhi_ep_ring_worker(struct work_struct *work) >>> } >>> } >>> +static void mhi_ep_queue_channel_db(struct mhi_ep_cntrl *mhi_cntrl, >>> + unsigned long ch_int, u32 ch_idx) >>> +{ >>> + struct device *dev = &mhi_cntrl->mhi_dev->dev; >>> + struct mhi_ep_ring_item *item; >>> + struct mhi_ep_ring *ring; >>> + unsigned int i; >> >> Why not u32 i? And why is the ch_int argument unsigned long? The value >> passed in is a u32. >> > > for_each_set_bit() expects the 2nd argument to be of type "unsigned long". > > Thanks, > Mani