From: Alexandre Torgue <alexandre.torgue@st.com>
To: biao huang <biao.huang@mediatek.com>
Cc: Jose Abreu <joabreu@synopsys.com>, <davem@davemloft.net>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
<netdev@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <yt.shen@mediatek.com>,
<jianguo.zhang@mediatek.com>
Subject: Re: [PATCH 2/6] net: stmmac: fix csr_clk can't be zero issue
Date: Mon, 29 Apr 2019 10:26:52 +0200 [thread overview]
Message-ID: <738b37cd-4719-9257-18fc-aab1dc7424f4@st.com> (raw)
In-Reply-To: <1556525353.24897.30.camel@mhfsdcap03>
On 4/29/19 10:09 AM, biao huang wrote:
> Hi,
>
> On Mon, 2019-04-29 at 09:18 +0200, Alexandre Torgue wrote:
>> Hi
>>
>> On 4/28/19 8:30 AM, Biao Huang wrote:
>>> The specific clk_csr value can be zero, and
>>> stmmac_clk is necessary for MDC clock which can be set dynamically.
>>> So, change the condition from plat->clk_csr to plat->stmmac_clk to
>>> fix clk_csr can't be zero issue.
>>>
>>> Signed-off-by: Biao Huang <biao.huang@mediatek.com>
>>> ---
>>> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>>> index 818ad88..9e89b94 100644
>>> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>>> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>>> @@ -4376,7 +4376,7 @@ int stmmac_dvr_probe(struct device *device,
>>> * set the MDC clock dynamically according to the csr actual
>>> * clock input.
>>> */
>>> - if (!priv->plat->clk_csr)
>>> + if (priv->plat->stmmac_clk)
>>> stmmac_clk_csr_set(priv);
>>> else
>>> priv->clk_csr = priv->plat->clk_csr;
>>>
>>
>> So, as soon as stmmac_clk will be declared, it is no longer possible to
>> fix a CSR through the device tree ?
>
> let's focus on the condition:
> 1. clk_csr may be zero, it should not be the condition. or the clk_csr =
> 0 will jump to the wrong block.
> 2. Since stmmac_clk_csr_set will get_clk_rate from stmmac_clk,
> the plat->stmmac_clk is a more proper condition.
>
Ok, but here you remove one possibility: stmmac_clk and clk_csr defined.
no ?
Other way could be the following code + initialize priv->plat->clk_csr
with a non null value before read it in device tree (in stmmac_platform).
if (priv->plat->clk_csr >= 0)
priv->clk_csr = priv->plat->clk_csr;
else
stmmac_clk_csr_set(priv);
> In some case, it's impossible to get the clk rate of stmmac_clk,
> so it's better to remain the clk_csr flow.
>
>
>
next prev parent reply other threads:[~2019-04-29 8:27 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-28 6:30 [PATCH 0/6] fix some bugs and add some features in stmmac Biao Huang
2019-04-28 6:30 ` [PATCH 1/6] net: stmmac: update rx tail pointer register to fix rx dma hang issue Biao Huang
2019-04-28 6:30 ` [PATCH 2/6] net: stmmac: fix csr_clk can't be zero issue Biao Huang
2019-04-29 7:18 ` Alexandre Torgue
2019-04-29 8:09 ` biao huang
2019-04-29 8:26 ` Alexandre Torgue [this message]
2019-04-30 9:15 ` biao huang
2019-04-30 9:43 ` Alexandre Torgue
2019-04-28 6:30 ` [PATCH 3/6] net: stmmac: write the modified value back to MTL_OPERATION_MODE Biao Huang
2019-04-28 6:30 ` [PATCH 4/6] net: stmmac: add support for hash table size 128/256 in dwmac4 Biao Huang
2019-04-28 6:30 ` [PATCH 5/6] net: stmmac: add mdio clause 45 access from mac device for dwmac4 Biao Huang
2019-04-28 16:37 ` Andrew Lunn
2019-04-29 6:05 ` biao huang
2019-04-29 13:23 ` Andrew Lunn
2019-04-28 6:30 ` [PATCH 6/6] stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail Biao Huang
2019-04-28 12:48 ` [PATCH 0/6] fix some bugs and add some features in stmmac David Miller
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