From: okukatla@codeaurora.org
To: Stephen Boyd <swboyd@chromium.org>
Cc: Andy Gross <agross@kernel.org>, Rob Herring <robh+dt@kernel.org>,
bjorn.andersson@linaro.org, devicetree@vger.kernel.org,
evgreen@google.com, georgi.djakov@linaro.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
seansw@qti.qualcomm.com, elder@linaro.org,
linux-pm@vger.kernel.org, linux-arm-msm-owner@vger.kernel.org
Subject: Re: [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
Date: Mon, 09 Aug 2021 22:17:18 +0530 [thread overview]
Message-ID: <74e3a26642342e88cb93c4e1aee62705@codeaurora.org> (raw)
In-Reply-To: <CAE-0n52XPJ7COZc7Zy=721-FGPX9D=vSFR_qccL86UXuABuy9Q@mail.gmail.com>
On 2021-07-09 04:34, Stephen Boyd wrote:
> Quoting Odelu Kukatla (2021-06-18 04:28:54)
>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>> SoCs.
>>
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 38a7f55..7690d7e 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -1153,6 +1153,15 @@
>> };
>> };
>>
>> + epss_l3: interconnect@18590000 {
>> + compatible = "qcom,sc7280-epss-l3";
>> + reg = <0 0x18590000 0 1000>, <0 0x18591000 0
>> 0x100>,
>> + <0 0x18592000 0 0x100>, <0 0x18593000
>> 0 0x100>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc
>> GCC_GPLL0>;
>> + clock-names = "xo", "alternate";
>> + #interconnect-cells = <1>;
>> + };
>
> Is this inside the soc node? Because it should be but then the next
> node
> is called 'interconnect' and has no address so that is probably outside
> the soc node. Please put nodes with a reg property like this into the
> soc node.
>
no, will move this into soc node in v5.
>> +
>> clk_virt: interconnect {
>> compatible = "qcom,sc7280-clk-virt";
>> #interconnect-cells = <2>;
prev parent reply other threads:[~2021-08-09 16:47 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-18 11:28 [V4 0/3] Add L3 provider support for SC7280 Odelu Kukatla
2021-06-18 11:28 ` [V4 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
2021-07-08 23:22 ` Stephen Boyd
2021-08-09 16:31 ` okukatla
2021-06-18 11:28 ` [V4 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla
2021-07-08 23:21 ` Stephen Boyd
2021-08-09 16:45 ` okukatla
2021-06-18 11:28 ` [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
2021-07-08 23:04 ` Stephen Boyd
2021-08-09 16:47 ` okukatla [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=74e3a26642342e88cb93c4e1aee62705@codeaurora.org \
--to=okukatla@codeaurora.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=elder@linaro.org \
--cc=evgreen@google.com \
--cc=georgi.djakov@linaro.org \
--cc=linux-arm-msm-owner@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=seansw@qti.qualcomm.com \
--cc=swboyd@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).