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[92.233.226.227]) by smtp.googlemail.com with ESMTPSA id e12sm3680787wrs.67.2021.01.27.09.48.48 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jan 2021 09:48:49 -0800 (PST) Subject: Re: [PATCH v2] ASoC: qcom: lpass-cpu: Remove bit clock state check To: Srinivasa Rao Mandadapu , agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz, tiwai@suse.com, rohitkr@codeaurora.org, linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20210127151824.8929-1-srivasam@codeaurora.org> From: Srinivas Kandagatla Message-ID: <752d2980-2c84-c03f-7960-b9de8027c4d6@linaro.org> Date: Wed, 27 Jan 2021 17:48:48 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20210127151824.8929-1-srivasam@codeaurora.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/01/2021 15:18, Srinivasa Rao Mandadapu wrote: > No need of BCLK state maintenance from driver side as > clock_enable and clk_disable API's maintaing state counter. > > One of the major issue was spotted when Headset jack inserted > while playback continues, due to same PCM device node opens twice > for playaback/capture and closes once for capture and playback continues. > > It can resolve the errors in such scenarios. > > Fixes: b1824968221c ("ASoC: qcom: Fix enabling BCLK and LRCLK in LPAIF invalid state") > > Signed-off-by: Srinivasa Rao Mandadapu Reviewed-by: Srinivas Kandagatla > --- > Changes since v1: > -- Commit message changed > > sound/soc/qcom/lpass-cpu.c | 22 ++++++++-------------- > sound/soc/qcom/lpass-lpaif-reg.h | 3 --- > sound/soc/qcom/lpass.h | 1 - > 3 files changed, 8 insertions(+), 18 deletions(-) > > diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c > index ae8efbc89af2..a669202e0001 100644 > --- a/sound/soc/qcom/lpass-cpu.c > +++ b/sound/soc/qcom/lpass-cpu.c > @@ -286,16 +286,12 @@ static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream, > dev_err(dai->dev, "error writing to i2sctl reg: %d\n", > ret); > > - if (drvdata->bit_clk_state[id] == LPAIF_BIT_CLK_DISABLE) { > - ret = clk_enable(drvdata->mi2s_bit_clk[id]); > - if (ret) { > - dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); > - clk_disable(drvdata->mi2s_osr_clk[id]); > - return ret; > - } > - drvdata->bit_clk_state[id] = LPAIF_BIT_CLK_ENABLE; > + ret = clk_enable(drvdata->mi2s_bit_clk[id]); > + if (ret) { > + dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); > + clk_disable(drvdata->mi2s_osr_clk[id]); > + return ret; > } > - > break; > case SNDRV_PCM_TRIGGER_STOP: > case SNDRV_PCM_TRIGGER_SUSPEND: > @@ -310,10 +306,9 @@ static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream, > if (ret) > dev_err(dai->dev, "error writing to i2sctl reg: %d\n", > ret); > - if (drvdata->bit_clk_state[id] == LPAIF_BIT_CLK_ENABLE) { > - clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]); > - drvdata->bit_clk_state[id] = LPAIF_BIT_CLK_DISABLE; > - } > + > + clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]); > + > break; > } > > @@ -861,7 +856,6 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) > PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); > return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); > } > - drvdata->bit_clk_state[dai_id] = LPAIF_BIT_CLK_DISABLE; > } > > /* Allocation for i2sctl regmap fields */ > diff --git a/sound/soc/qcom/lpass-lpaif-reg.h b/sound/soc/qcom/lpass-lpaif-reg.h > index 405542832e99..c8e1d75340b2 100644 > --- a/sound/soc/qcom/lpass-lpaif-reg.h > +++ b/sound/soc/qcom/lpass-lpaif-reg.h > @@ -60,9 +60,6 @@ > #define LPAIF_I2SCTL_BITWIDTH_24 1 > #define LPAIF_I2SCTL_BITWIDTH_32 2 > > -#define LPAIF_BIT_CLK_DISABLE 0 > -#define LPAIF_BIT_CLK_ENABLE 1 > - > #define LPAIF_I2SCTL_RESET_STATE 0x003C0004 > #define LPAIF_DMACTL_RESET_STATE 0x00200000 > > diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h > index 2d68af0da34d..83b2e08ade06 100644 > --- a/sound/soc/qcom/lpass.h > +++ b/sound/soc/qcom/lpass.h > @@ -68,7 +68,6 @@ struct lpass_data { > unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS]; > unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS]; > int hdmi_port_enable; > - int bit_clk_state[LPASS_MAX_MI2S_PORTS]; > > /* low-power audio interface (LPAIF) registers */ > void __iomem *lpaif; >