From: Alexandre Torgue <alexandre.torgue@st.com>
To: Arnd Bergmann <arnd@arndb.de>,
Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Russell King - ARM Linux <linux@armlinux.org.uk>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>
Subject: Re: [PATCH 0/2] ARM errata 814220
Date: Fri, 15 Feb 2019 17:30:44 +0100 [thread overview]
Message-ID: <755c9689-9027-b085-d511-05d833d1e6ef@st.com> (raw)
In-Reply-To: <CAK8P3a0mbEqfzQhP0qX3kSnErBLws9ojkmbVQng9HhujFLCMvA@mail.gmail.com>
On 2/13/19 3:52 PM, Arnd Bergmann wrote:
> On Wed, Feb 13, 2019 at 10:56 AM Benjamin Gaignard
> <benjamin.gaignard@linaro.org> wrote:
>>
>> Implement ARM errata 814220 for Cortex A7.
>>
>> This patch has been wroten by Jason Liu years ago but never send upstream.
>> I have tried to contact the author on multiple email addresses but I haven't
>> found any valid one...
>> I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
>>
>> Benjamin Gaignard (2):
>> ARM: errata 814220-B-Cache maintenance by set/way operations can
>> execute out of order.
>> ARM: stm32: select ARM errata 814220
>>
>> arch/arm/Kconfig | 10 ++++++++++
>> arch/arm/mach-stm32/Kconfig | 1 +
>> arch/arm/mm/cache-v7.S | 3 +++
>> 3 files changed, 14 insertions(+)
>
> Looks good to me,
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
>
> It probably makes most sense to keep them as a series, either
> through the soc tree or Russell's patch tracker, so feel free to add
> it there, and have them both in the stm32 soc branch for arm-soc
> if Russell prefers.
Russel, what do you think about Arnd proposition? I could take both
patches in my stm32 tree. It'll make part of future v5.2 pull request.
Alex
>
> As we have a number of Cortex-A7 based platforms with all
> kinds of revisions, I wonder if we should also select the workaround
> for the others. I can probably figure out which SoC platforms
> are based on Cortex-A7, but I have no idea about the revisions,
> so that might mean we'd have to do it for all of them. According
> to the latest TRM I found, only revisions r0p0 through r0p5
> exist, and the erraturm text lists r0p2 through r0p5, which may
> mean all products ever shipped in practice (the oldest public
> TRM from 2012 already describe r0p3).
>
>
>
>
> Arnd
>
prev parent reply other threads:[~2019-02-15 16:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-13 9:56 [PATCH 0/2] ARM errata 814220 Benjamin Gaignard
2019-02-13 9:56 ` [PATCH 1/2] ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order Benjamin Gaignard
2019-02-13 18:27 ` Russell King - ARM Linux admin
2019-02-13 9:56 ` [PATCH 2/2] ARM: stm32: select ARM errata 814220 Benjamin Gaignard
2019-02-13 14:52 ` [PATCH 0/2] " Arnd Bergmann
2019-02-15 16:30 ` Alexandre Torgue [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=755c9689-9027-b085-d511-05d833d1e6ef@st.com \
--to=alexandre.torgue@st.com \
--cc=arnd@arndb.de \
--cc=benjamin.gaignard@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-stm32@st-md-mailman.stormreply.com \
--cc=linux@armlinux.org.uk \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).