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Tue, 19 Mar 2024 12:16:16 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42JCGF8K002516 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Mar 2024 12:16:15 GMT Received: from [10.216.16.222] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 19 Mar 2024 05:16:08 -0700 Message-ID: <756ccc79-0077-5c23-73e3-bbb82fbfa8b0@quicinc.com> Date: Tue, 19 Mar 2024 17:46:05 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v4 2/5] drivers: mtd: nand: Add qpic_common API file Content-Language: en-US To: Miquel Raynal CC: , , , , , , , , , , , , , , , , , , , , References: <20240308091752.16136-1-quic_mdalam@quicinc.com> <20240308091752.16136-3-quic_mdalam@quicinc.com> <20240315124517.4a546ce9@xps-13> <93b08226-3297-2161-cc7d-d33d839c32f0@quicinc.com> <20240319114316.4b977d93@xps-13> From: Md Sadre Alam In-Reply-To: <20240319114316.4b977d93@xps-13> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: EHsv-UYCpwLm-waElPxoZGnYSzU6NkYY X-Proofpoint-ORIG-GUID: EHsv-UYCpwLm-waElPxoZGnYSzU6NkYY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-19_02,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 mlxlogscore=650 spamscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403140001 definitions=main-2403190094 On 3/19/2024 4:13 PM, Miquel Raynal wrote: > Hi, > >>>> +/** >>>> + * qcom_offset_to_nandc_reg() - Get the actual offset >>>> + * @regs: pointer to nandc_reg structure >>>> + * @offset: register offset >>>> + * >>>> + * This function will reurn the actual offset for qpic controller register >>>> + */ >>>> +__le32 *qcom_offset_to_nandc_reg(struct nandc_regs *regs, int offset) >>>> +{ >>>> + switch (offset) { >>>> + case NAND_FLASH_CMD: >>>> + return ®s->cmd; >>>> + case NAND_ADDR0: >>>> + return ®s->addr0; >>>> + case NAND_ADDR1: >>>> + return ®s->addr1; >>>> + case NAND_FLASH_CHIP_SELECT: >>>> + return ®s->chip_sel; >>>> + case NAND_EXEC_CMD: >>>> + return ®s->exec; >>>> + case NAND_FLASH_STATUS: >>>> + return ®s->clrflashstatus; >>>> + case NAND_DEV0_CFG0: >>>> + return ®s->cfg0; >>>> + case NAND_DEV0_CFG1: >>>> + return ®s->cfg1; >>>> + case NAND_DEV0_ECC_CFG: >>>> + return ®s->ecc_bch_cfg; >>>> + case NAND_READ_STATUS: >>>> + return ®s->clrreadstatus; >>>> + case NAND_DEV_CMD1: >>>> + return ®s->cmd1; >>>> + case NAND_DEV_CMD1_RESTORE: >>>> + return ®s->orig_cmd1; >>>> + case NAND_DEV_CMD_VLD: >>>> + return ®s->vld; >>>> + case NAND_DEV_CMD_VLD_RESTORE: >>>> + return ®s->orig_vld; >>>> + case NAND_EBI2_ECC_BUF_CFG: >>>> + return ®s->ecc_buf_cfg; >>>> + case NAND_READ_LOCATION_0: >>>> + return ®s->read_location0; >>>> + case NAND_READ_LOCATION_1: >>>> + return ®s->read_location1; >>>> + case NAND_READ_LOCATION_2: >>>> + return ®s->read_location2; >>>> + case NAND_READ_LOCATION_3: >>>> + return ®s->read_location3; >>>> + case NAND_READ_LOCATION_LAST_CW_0: >>>> + return ®s->read_location_last0; >>>> + case NAND_READ_LOCATION_LAST_CW_1: >>>> + return ®s->read_location_last1; >>>> + case NAND_READ_LOCATION_LAST_CW_2: >>>> + return ®s->read_location_last2; >>>> + case NAND_READ_LOCATION_LAST_CW_3: >>>> + return ®s->read_location_last3; >>> >>> Why do you need this indirection? >> >> This indirection I believe is needed by the write_reg_dma function, >> wherein a bunch of registers are modified based on a starting register. >> Can I change this in a separate cleanup series as a follow up to this? > > I think it would be cleaner to make the changes I requested first and > then make a copy. I understand it is more work on your side, so if you > really prefer you can (1) make the copy and then (2) clean it all. But > please do it all in this series. Ok > >>>> diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h >>>> new file mode 100644 >>>> index 000000000000..aced15866627 >>>> --- /dev/null >>>> +++ b/include/linux/mtd/nand-qpic-common.h >>>> @@ -0,0 +1,486 @@ >>>> +/* SPDX-License-Identifier: GPL-2.0 */ >>>> +/* >>>> + * QCOM QPIC common APIs header file >>>> + * >>>> + * Copyright (c) 2023 Qualcomm Inc. >>>> + * Authors: Md sadre Alam >>>> + * Sricharan R >>>> + * Varadarajan Narayanan >>>> + * >>>> + */ >>>> +#ifndef __MTD_NAND_QPIC_COMMON_H__ >>>> +#define __MTD_NAND_QPIC_COMMON_H__ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>> >>> You really need this? >> Yes , since some generic structure used here. > > Which ones? If this is a common file, you probably should not. Since we are using this struct qcom_nand_controller { } for both SPI nand as well as raw nand. In this we are having this struct nand_controller controller member. > > Thanks, > Miquèl Thanks, Alam.