From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20D71C43216 for ; Mon, 23 Aug 2021 21:20:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 09F5F613A8 for ; Mon, 23 Aug 2021 21:20:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232859AbhHWVVJ (ORCPT ); Mon, 23 Aug 2021 17:21:09 -0400 Received: from gloria.sntech.de ([185.11.138.130]:54948 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232921AbhHWVU6 (ORCPT ); Mon, 23 Aug 2021 17:20:58 -0400 Received: from p5b036204.dip0.t-ipconnect.de ([91.3.98.4] helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mIHMW-0002ta-Ce; Mon, 23 Aug 2021 23:20:08 +0200 From: Heiko Stuebner To: Alex Bee Cc: Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: rockchip: Fix GPU register width for RK3328 Date: Mon, 23 Aug 2021 23:20:04 +0200 Message-ID: <7657417.31r3eYUQgx@phil> In-Reply-To: References: <20210623115926.164861-1-knaerzche@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Alex, Am Montag, 23. August 2021, 00:19:08 CEST schrieb Alex Bee: > Hi Heiko, > > is there anything left to do for this one? nope, there wasn't anything missing, I just somehow managed to overlook the patch till your ping. As you can see from the other mail, it is applied now :-) Heiko > > Same for: > > https://patchwork.kernel.org/project/linux-rockchip/patch/20210623145918.187018-1-knaerzche@gmail.com/ > > and > > https://patchwork.kernel.org/project/linux-rockchip/patch/20210623150208.187201-1-knaerzche@gmail.com/ > > Alex > > Am 23.06.21 um 13:59 schrieb Alex Bee: > > As can be seen in RK3328's TRM the register range for the GPU is > > 0xff300000 to 0xff330000. > > It would (and does in vendor kernel) overlap with the registers of > > the HEVC encoder (node/driver do not exist yet in upstream kernel). > > See already existing h265e_mmu node. > > > > Fixes: 752fbc0c8da7 ("arm64: dts: rockchip: add rk3328 mali gpu node") > > Signed-off-by: Alex Bee > > --- > > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > > index 8c821acb21ff..da84be6f4715 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > > @@ -599,7 +599,7 @@ saradc: adc@ff280000 { > > > > gpu: gpu@ff300000 { > > compatible = "rockchip,rk3328-mali", "arm,mali-450"; > > - reg = <0x0 0xff300000 0x0 0x40000>; > > + reg = <0x0 0xff300000 0x0 0x30000>; > > interrupts = , > > , > > , >