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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH RESEND v2 3/3] dmaengine: tegra: Add support for dma-channel-mask Content-Language: en-US To: Akhil R , Rob Herring Cc: Laxman Dewangan , "vkoul@kernel.org" , "thierry.reding@gmail.com" , "p.zabel@pengutronix.de" , "dmaengine@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "sfr@canb.auug.org.au" References: <20221020083322.36431-1-akhilrajeev@nvidia.com> <20221020083322.36431-4-akhilrajeev@nvidia.com> <20221021021604.GA2181729-robh@kernel.org> From: Jon Hunter In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: LO4P265CA0134.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:2c4::6) To CO6PR12MB5444.namprd12.prod.outlook.com (2603:10b6:5:35e::8) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO6PR12MB5444:EE_|IA1PR12MB6410:EE_ X-MS-Office365-Filtering-Correlation-Id: 5eaed7ce-0fea-494f-ecdf-08dab734c316 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This helps to reserve some channels for the firmware. >>> >>> This was initially achieved by limiting the channel number to 31 in >>> the driver and adjusting the register address to skip channel0 which >>> was reserved for a firmware. Now, with this change, the driver can >>> align more to the actual hardware which has 32 channels. >>> >>> Signed-off-by: Akhil R >>> Reviewed-by: Jon Hunter >>> --- >>> drivers/dma/tegra186-gpc-dma.c | 37 +++++++++++++++++++++++++++------- >>> 1 file changed, 30 insertions(+), 7 deletions(-) >>> >>> diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc- >> dma.c >>> index fa9bda4a2bc6..1d1180db6d4e 100644 >>> --- a/drivers/dma/tegra186-gpc-dma.c >>> +++ b/drivers/dma/tegra186-gpc-dma.c >>> @@ -161,7 +161,10 @@ >>> #define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 5000 /* 5 >> msec */ >>> >>> /* Channel base address offset from GPCDMA base address */ >>> -#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x20000 >>> +#define TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET 0x10000 >>> + >>> +/* Default channel mask reserving channel0 */ >>> +#define TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK 0xfffffffe >>> >>> struct tegra_dma; >>> struct tegra_dma_channel; >>> @@ -246,6 +249,7 @@ struct tegra_dma { >>> const struct tegra_dma_chip_data *chip_data; >>> unsigned long sid_m2d_reserved; >>> unsigned long sid_d2m_reserved; >>> + u32 chan_mask; >>> void __iomem *base_addr; >>> struct device *dev; >>> struct dma_device dma_dev; >>> @@ -1288,7 +1292,7 @@ static struct dma_chan *tegra_dma_of_xlate(struct >> of_phandle_args *dma_spec, >>> } >>> >>> static const struct tegra_dma_chip_data tegra186_dma_chip_data = { >>> - .nr_channels = 31, >>> + .nr_channels = 32, >> >> This is an ABI break. A new kernel with an old DTB will use 32 channels >> instead of 31. You should leave this and use the dma-channel-mask to >> enable all 32 channels. >> > Hi Rob, > > If using an old DTB, tdma->chan_mask will be default to 0xfffffffe since it > would not have the dma-channel-mask property. The driver would still > use 31 channels even if it uses an old DTB. Shouldn't it prevent the > ABI break? Unfortunately no. Yes for an old DTB without the dma-channel-mask property, we set the channel mask to 0xfffffffe, but this is not correct because it only has 31 interrupts/channels and not 32. So I think we will need to use of_irq_count() here. Jon -- nvpublic