From: Reinette Chatre <reinette.chatre@intel.com>
To: "Moger, Babu" <Babu.Moger@amd.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
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Subject: Re: [RFC PATCH 10/10] arch/x86: Introduce QOS feature for AMD
Date: Tue, 2 Oct 2018 15:13:02 -0700 [thread overview]
Message-ID: <7690b121-dd54-ea58-ec77-2dbb88c25b16@intel.com> (raw)
In-Reply-To: <20180924191841.29111-11-babu.moger@amd.com>
Hi Babu,
On 9/24/2018 12:19 PM, Moger, Babu wrote:
> +/*
> + * Check whether a cache bit mask is valid. AMD allows
> + * non-contiguous masks.
> + */
> +bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r)
> +{
> + unsigned long first_bit, zero_bit, val;
> + unsigned int cbm_len = r->cache.cbm_len;
> + int ret;
> +
> + ret = kstrtoul(buf, 16, &val);
> + if (ret) {
> + rdt_last_cmd_printf("non-hex character in mask %s\n", buf);
> + return false;
> + }
> +
> + if (val == 0 || val > r->default_ctrl) {
> + rdt_last_cmd_puts("mask out of range\n");
> + return false;
> + }
According to
https://www.amd.com/system/files/TechDocs/56375_Quality_of_Service_Extensions.pdf
"If an L3_MASK_n register is programmed with all 0’s, that COS will be
prevented from allocating any lines in the L3 cache."
The "val == 0" test thus does not seem necessary.
> +
> + first_bit = find_first_bit(&val, cbm_len);
> + zero_bit = find_next_zero_bit(&val, cbm_len, first_bit);
> +
> +
> + if ((zero_bit - first_bit) < r->cache.min_cbm_bits) {
> + rdt_last_cmd_printf("Need at least %d bits in mask\n",
> + r->cache.min_cbm_bits);
> + return false;
> + }
If AMD platforms accept CBM of all zeroes then it seems that the
platforms would not require a minimum number of set bits?
Reinette
next prev parent reply other threads:[~2018-10-02 22:13 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-24 19:18 [RFC PATCH 00/10] arch/x86: AMD QoS support Moger, Babu
2018-09-24 19:18 ` [RFC PATCH 01/10] arch/x86: Start renaming the rdt files to more generic names Moger, Babu
2018-09-24 19:18 ` [RFC PATCH 02/10] arch/x86: Rename the RDT functions and definitions Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 03/10] arch/x86: Re-arrange RDT init code Moger, Babu
2018-10-02 19:21 ` Reinette Chatre
2018-10-02 23:41 ` Moger, Babu
2018-10-03 18:54 ` Reinette Chatre
2018-10-03 20:12 ` Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 04/10] arch/x86: Introduce a new config parameter PLATFORM_QOS Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 05/10] arch/x86: Use new config parameter PLATFORM_QOS for compilation Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 06/10] arch/x86: Initialize the resource functions that are different Moger, Babu
2018-10-02 22:06 ` Reinette Chatre
2018-10-03 15:25 ` Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 07/10] arch/x86: Bring few more functions into the resource structure Moger, Babu
2018-10-02 22:07 ` Reinette Chatre
2018-10-03 15:32 ` Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 08/10] arch/x86: Introduce new config parameter AMD_QOS Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 09/10] arch/x86: Add AMD feature bit X86_FEATURE_MBA in cpuid bits array Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 10/10] arch/x86: Introduce QOS feature for AMD Moger, Babu
2018-10-02 18:27 ` Fenghua Yu
2018-10-03 15:56 ` Moger, Babu
2018-10-02 22:13 ` Reinette Chatre [this message]
2018-10-03 17:21 ` Moger, Babu
2018-10-05 16:20 ` James Morse
2018-10-05 17:18 ` Moger, Babu
2018-09-27 20:14 ` [RFC PATCH 00/10] arch/x86: AMD QoS support Thomas Gleixner
2018-09-28 1:57 ` Moger, Babu
2018-10-05 16:18 ` James Morse
2018-10-05 17:03 ` Moger, Babu
2018-10-02 17:06 ` Fenghua Yu
2018-10-02 17:44 ` Moger, Babu
2018-10-02 18:46 ` Fenghua Yu
2018-10-02 19:16 ` Moger, Babu
2018-10-03 18:52 ` Fenghua Yu
2018-10-03 19:48 ` Thomas Gleixner
2018-10-03 20:09 ` Moger, Babu
2018-10-05 16:19 ` James Morse
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