From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D728C4332F for ; Tue, 5 Oct 2021 20:56:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 253F26121F for ; Tue, 5 Oct 2021 20:56:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236525AbhJEU6L (ORCPT ); Tue, 5 Oct 2021 16:58:11 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:11331 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236447AbhJEU6J (ORCPT ); Tue, 5 Oct 2021 16:58:09 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1633467379; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=d2UIVnPOW3ElF02gfggo+xeMDHqG4QtmTz1NBPCyNOc=; b=g63ZB6BczuWWO0MZG9ebm9evow6YvIZlbJi1eKjAUMnqaHLUdnTkSzF4tg2FLRPqZuDQ8Z3n smyYKAngNISOLBjZzrVv3Pg00nmzWSFu/OfhUkohf0x7x6Y1+RKOlgey9OTf1ui+IQ3jQTHH 0vyC0OWpjzs742BMmURiBs/u1sM= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-east-1.postgun.com with SMTP id 615cbbf29ebaf35aaa14b507 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 05 Oct 2021 20:56:18 GMT Sender: abhinavk=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 60C9DC4361B; Tue, 5 Oct 2021 20:56:17 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: abhinavk) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6416DC43460; Tue, 5 Oct 2021 20:56:16 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Tue, 05 Oct 2021 13:56:16 -0700 From: abhinavk@codeaurora.org To: Bjorn Andersson Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: Re: [Freedreno] [PATCH v3 1/5] dt-bindings: msm/dp: Change reg definition In-Reply-To: <20211001174400.981707-2-bjorn.andersson@linaro.org> References: <20211001174400.981707-1-bjorn.andersson@linaro.org> <20211001174400.981707-2-bjorn.andersson@linaro.org> Message-ID: <78cc9c0faafcab3375f74a4f52790a52@codeaurora.org> X-Sender: abhinavk@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021-10-01 10:43, Bjorn Andersson wrote: > reg was defined as one region covering the entire DP block, but the > memory map is actually split in 4 regions and obviously the size of > these regions differs between platforms. > > Switch the reg to require that all four regions are specified instead. > It is expected that the implementation will handle existing DTBs, even > though the schema defines the new layout. > > Reviewed-by: Stephen Boyd > Reviewed-by: Rob Herring > Signed-off-by: Bjorn Andersson Reviewed-by: Abhinav Kumar > --- > > Changes since v2: > - None > > .../bindings/display/msm/dp-controller.yaml | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > index d89b3c510c27..6bb424c21340 100644 > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > @@ -19,7 +19,12 @@ properties: > - qcom,sc7180-dp > > reg: > - maxItems: 1 > + items: > + - description: ahb register block > + - description: aux register block > + - description: link register block > + - description: p0 register block > + - description: p1 register block > > interrupts: > maxItems: 1 > @@ -99,7 +104,11 @@ examples: > > displayport-controller@ae90000 { > compatible = "qcom,sc7180-dp"; > - reg = <0xae90000 0x1400>; > + reg = <0xae90000 0x200>, > + <0xae90200 0x200>, > + <0xae90400 0xc00>, > + <0xae91000 0x400>, > + <0xae91400 0x400>; > interrupt-parent = <&mdss>; > interrupts = <12>; > clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,