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[86.26.103.58]) by smtp.googlemail.com with ESMTPSA id n8-20020a5d4848000000b00226d01a4635sm9658965wrs.35.2022.08.30.06.37.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Aug 2022 06:37:42 -0700 (PDT) Message-ID: <791ea3b6-c326-9e71-e23b-93206e305c85@linaro.org> Date: Tue, 30 Aug 2022 14:37:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v1 00/14] nvmem: core: introduce NVMEM layouts Content-Language: en-US To: Michael Walle , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= Cc: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Li Yang , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Frank Rowand , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, Ahmad Fatoum References: <20220825214423.903672-1-michael@walle.cc> <768ff63a-54f5-9cde-e888-206cdf018df3@milecki.pl> <267821eee5dcab79fd0ecebe0d9f8b0c@walle.cc> From: Srinivas Kandagatla In-Reply-To: <267821eee5dcab79fd0ecebe0d9f8b0c@walle.cc> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks Michael for the work. On 29/08/2022 09:22, Michael Walle wrote: > >> One thing I believe you need to handle is replacing "cell_post_process" >> callback with your layout thing. >> >> I find it confusing to have >> 1. cell_post_process() CB at NVMEM device level >> 2. post_process() CB at NVMEM cell level > > What is wrong with having a callback at both levels? we should converge this tbh, its more than one code paths to deal with similar usecases. I have put down some thoughts in "[PATCH v1 06/14] nvmem: core: introduce NVMEM layouts" and "[PATCH v1 07/14] nvmem: core: add per-cell post processing" review. --srini > > Granted, in this particular case (it is just used at one place), I still > think that it is the wrong approach to add this transformation in the > driver (in this particular case). The driver is supposed to give you > access to the SoC's fuse box, but it will magically change the content > of a cell if the nvmem consumer named this cell "mac-address" (which > you also found confusing the last time and I do too!). > > The driver itself doesn't add any cells on its own, so I cannot register > a .post_process hook there. Therefore, you'd need that post_process hook > on every cell, which is equivalent to have a post_process hook at > device level. > > Unless you have a better idea. I'll leave that up to NXP to fix that (or > leave it like that). > > -michael