From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-23.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DA15C433DB for ; Sat, 30 Jan 2021 23:55:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1BB8C64E0C for ; Sat, 30 Jan 2021 23:55:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232746AbhA3Xyp (ORCPT ); Sat, 30 Jan 2021 18:54:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232653AbhA3XxH (ORCPT ); Sat, 30 Jan 2021 18:53:07 -0500 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 349A8C0613ED for ; Sat, 30 Jan 2021 15:51:45 -0800 (PST) Received: by mail-pf1-x42e.google.com with SMTP id o20so9069055pfu.0 for ; Sat, 30 Jan 2021 15:51:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:from:to:cc:subject:in-reply-to:message-id:references :mime-version; bh=GDv15DwnRp3MS5y0X9bL9QkhV0S8PjNmrscexBhhUtA=; b=Mniksk0+xMkFOMZyyZxYvBktssUOJFhazgAfgAHn9e+16eIYt+3GlpWg6E0DAJ8fYY WDuDlRb+ul9uZLNgaLXC4pv8dqBpjAjemOJWnSsOSyiy69MNK+dOs/FZDn7dLcxhzUNS 59fLeXPXG9kHc1/bO/wl17ZNmqBSO12pGkj4fTSPU8f8wXSUykglI65cZ1o3wa7S+uC7 WjnOnqrs8SPFn6yfNbHYcMWzjiHuBQaWXhxy6t+TrLWD5+PfN1LqKdWyN5QyGpSwfr9m ec4kibCqC+jcrS3ail6HKNoQTR0CkaVYGqzRs/nXdEYb5wVMTjzQ8l7kqTklE8pFArx7 bm3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:in-reply-to:message-id :references:mime-version; bh=GDv15DwnRp3MS5y0X9bL9QkhV0S8PjNmrscexBhhUtA=; b=F81/ka7Ytw8jgeCOhrreR0QeVIOtZpY6H96/M2/M151XFlWJ3/DDgz/IflQ4BwgJOE BeHLbH5iS7ROSpGrjYKMLv4jonbvERWxnXqFL/JP5Hi6g1WnJwywrtgLhSbzKrpjHVII iqoZW5fWkWbATS1FqDVMW5W/URF4v6cBP47lRtE26mG05koV87XakvYRtAuA/vsOnzWf McdB9/pydLV+auSFFYe0jmDBWj2xJCl6TvwJ79MnsVuy+kolcwDtT+J9tRL2npwDH2kJ lRv1gyCZsScyNojwgoomglDWwI1PHkFaqnhFZI0nOkY5+bORcPHAwRp/O9GsYPiz+It5 TGbA== X-Gm-Message-State: AOAM530i2Po8WRm7knzJkKfTr5NttX2OgAHK63GLHTs21eMOJqg5Y6h0 WcDZLrBnev3AkChN1f6jqU/p5fdpg0++SA== X-Google-Smtp-Source: ABdhPJwbuQ4nVg0OQPgeWs57sXjRNYE2dA+6UJRCYf1jVILDhdLj6k91Bbw9k3VuSrWFNKVhFs7mpg== X-Received: by 2002:a63:f405:: with SMTP id g5mr10896366pgi.276.1612050704574; Sat, 30 Jan 2021 15:51:44 -0800 (PST) Received: from [2620:15c:17:3:4a0f:cfff:fe51:6667] ([2620:15c:17:3:4a0f:cfff:fe51:6667]) by smtp.gmail.com with ESMTPSA id a25sm12812739pgv.40.2021.01.30.15.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Jan 2021 15:51:43 -0800 (PST) Date: Sat, 30 Jan 2021 15:51:42 -0800 (PST) From: David Rientjes To: Ben Widawsky cc: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-nvdimm@lists.01.org, linux-pci@vger.kernel.org, Bjorn Helgaas , Chris Browy , Christoph Hellwig , Dan Williams , Ira Weiny , Jon Masters , Jonathan Cameron , Rafael Wysocki , Randy Dunlap , Vishal Verma , daniel.lll@alibaba-inc.com, "John Groves (jgroves)" , "Kelley, Sean V" Subject: Re: [PATCH 02/14] cxl/mem: Map memory device registers In-Reply-To: <20210130002438.1872527-3-ben.widawsky@intel.com> Message-ID: <792edaa-a11b-41c6-c2a1-2c72a3e4e815@google.com> References: <20210130002438.1872527-1-ben.widawsky@intel.com> <20210130002438.1872527-3-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 29 Jan 2021, Ben Widawsky wrote: > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > new file mode 100644 > index 000000000000..d81d0ba4617c > --- /dev/null > +++ b/drivers/cxl/cxl.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* Copyright(c) 2020 Intel Corporation. */ > + > +#ifndef __CXL_H__ > +#define __CXL_H__ > + > +/** > + * struct cxl_mem - A CXL memory device > + * @pdev: The PCI device associated with this CXL device. > + * @regs: IO mappings to the device's MMIO > + */ > +struct cxl_mem { > + struct pci_dev *pdev; > + void __iomem *regs; > +}; > + > +#endif Stupid question: can there be more than one CXL.mem capable logical device? I only ask to determine if an ordinal is needed to enumerate multiple LDs. > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index f4ee9a507ac9..a869c8dc24cc 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -4,6 +4,58 @@ > #include > #include > #include "pci.h" > +#include "cxl.h" > + > +/** > + * cxl_mem_create() - Create a new &struct cxl_mem. > + * @pdev: The pci device associated with the new &struct cxl_mem. > + * @reg_lo: Lower 32b of the register locator > + * @reg_hi: Upper 32b of the register locator. > + * > + * Return: The new &struct cxl_mem on success, NULL on failure. > + * > + * Map the BAR for a CXL memory device. This BAR has the memory device's > + * registers for the device as specified in CXL specification. > + */ > +static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev, u32 reg_lo, > + u32 reg_hi) > +{ > + struct device *dev = &pdev->dev; > + struct cxl_mem *cxlm; > + void __iomem *regs; > + u64 offset; > + u8 bar; > + int rc; > + > + offset = ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK); > + bar = (reg_lo >> CXL_REGLOC_BIR_SHIFT) & CXL_REGLOC_BIR_MASK; > + > + /* Basic sanity check that BAR is big enough */ > + if (pci_resource_len(pdev, bar) < offset) { > + dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, > + &pdev->resource[bar], (unsigned long long)offset); > + return NULL; > + } > + > + rc = pcim_iomap_regions(pdev, BIT(bar), pci_name(pdev)); > + if (rc != 0) { > + dev_err(dev, "failed to map registers\n"); > + return NULL; > + } > + > + cxlm = devm_kzalloc(&pdev->dev, sizeof(*cxlm), GFP_KERNEL); > + if (!cxlm) { > + dev_err(dev, "No memory available\n"); > + return NULL; > + } > + > + regs = pcim_iomap_table(pdev)[bar]; > + cxlm->pdev = pdev; > + cxlm->regs = regs + offset; > + > + dev_dbg(dev, "Mapped CXL Memory Device resource\n"); > + return cxlm; > +} > > static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) > { > @@ -32,15 +84,42 @@ static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) > static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id) > { > struct device *dev = &pdev->dev; > - int regloc; > + struct cxl_mem *cxlm; > + int rc, regloc, i; > + > + rc = pcim_enable_device(pdev); > + if (rc) > + return rc; > > regloc = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_CXL_REGLOC); > if (!regloc) { > dev_err(dev, "register location dvsec not found\n"); > return -ENXIO; > } > + regloc += 0xc; /* Skip DVSEC + reserved fields */ Assuming the DVSEC revision number is always 0x0 or there's no value in storing this in struct cxl_mem for the future. Acked-by: David Rientjes