From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752561AbbJFIDQ (ORCPT ); Tue, 6 Oct 2015 04:03:16 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:48556 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751612AbbJFIDH (ORCPT ); Tue, 6 Oct 2015 04:03:07 -0400 X-AuditID: cbfee68e-f791c6d000001498-86-5613803929c3 Date: Tue, 06 Oct 2015 08:03:05 +0000 (GMT) From: Sarbojit Ganguly Subject: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange To: Sarbojit Ganguly , Will Deacon Cc: "linux@arm.linux.org.uk" , "catalin.marinas@arm.com" , "Waiman.Long@hp.com" , "peterz@infradead.org" , VIKRAM MUPPARTHI , "linux-kernel@vger.kernel.org" , SUNEEL KUMAR SURIMANI , SHARAN ALLUR , "torvalds@linux-foundation.org" , "linux-arm-kernel@lists.infradead.org" Reply-to: ganguly.s@samsung.com MIME-version: 1.0 X-MTR: 20151006073739725@ganguly.s Msgkey: 20151006073739725@ganguly.s X-EPLocale: en_US.windows-1252 X-Priority: 3 X-EPWebmail-Msg-Type: personal X-EPWebmail-Reply-Demand: 0 X-EPApproval-Locale: X-EPHeader: ML X-MLAttribute: X-RootMTR: 20151006030518971@ganguly.s X-ParentMTR: 20151006030518971@ganguly.s X-ArchiveUser: X-CPGSPASS: Y X-ConfirmMail: N,general Content-type: text/plain; charset=windows-1252 MIME-version: 1.0 Message-id: <795992290.5810091444118582583.JavaMail.weblogic@epmlwas01d> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrCIsWRmVeSWpSXmKPExsWyRsSkRteyQTjM4MpucYvLu+awOTB6fN4k F8AYxWWTkpqTWZZapG+XwJVxbOZupoJl2hWbZv5mamCcotXFyMEhJKAi0TcpoouRk0NCwESi 5fU8VghbTOLCvfVsXYxcQCVLGSW2dbYzgdSDFP3vVYaIz2GUmNA5jRGkgQVozvXvc9hAbDYB fYnT+18ygdjCAqESvyf0MYPYIkD2+33rWEGamQVWskhM/3gMLCEkIC/R/mI7WAOvgKDEyZlP WCCWKUlc6BaHCCtLvFm5jRniODmJJVMvM0HYvBIz2p+ywMSnfV0DVSMtcX7WBkaYZxZ/fwwV 55c4dnsHVK+AxNQzB6Fq1CWaH5yHsjUlPn08ywJTv+vUcmaYXQ0bf7ND2BISW1uegAOLWUBR Ykr3Q3YI20DiyKI5rKheAbE9JBZ/ncsO8ruEwEQOicN9E9kmMCrNQlI3C8msWUhmIatZwMiy ilE0tSC5oDgpvchIrzgxt7g0L10vOT93EyMwMZz+96xvB+PNA9aHGAU4GJV4eCVuCoUJsSaW FVfmHmI0BcbTRGYp0eR8YPrJK4k3NDYzsjA1MTU2Mrc0UxLnTZD6GSwkkJ5YkpqdmlqQWhRf VJqTWnyIkYmDU6qBUUyZIcjPR4+nbvmpCxtb5q89XibWtkn8xd45MToP39eUH5qyhD/vy2HH +7OXL7kvKMfNwxufoPnYRIJNftPHgvqfQcde6k6c91dlaZ/dmo03Xmo3/NA41Xsl7jpv1uNJ a1/2P3r2UI11i8Bt3/x43XRlIWbWtcHtzIf5jr/q015v8KNhle7e80osxRmJhlrMRcWJABja cEwHAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKKsWRmVeSWpSXmKPExsVy+t/tfl3LBuEwg0v3eCwu75rD5sDo8XmT XABjVJpNRmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtBQ JYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUrShuZGekYGeqZGeoWmslaGBgZEpUE1CWsax mbuZCpZpV2ya+ZupgXGKVhcjB4eQgIpE36QIEFNCwETif69yFyMnkCkmceHeerYuRi6gijmM EhM6pzGCJFiAyq9/n8MGYrMJ6Euc3v+SCcQWFgiV+D2hjxnEFgGy3+9bxwrSzCywkkVi+sdj YAkhAXmJ9hfbwRp4BQQlTs58wgKxWEniQrc4RFhZ4s3KbcwQR8hJLJl6mQnC5pWY0f6UBSY+ 7esaqBppifOzNjDCHL34+2OoOL/Esds7oHoFJKaeOQhVoy7R/OA8lK0p8enjWRaY+l2nljPD 7GrY+JsdwpaQ2NryhBXEZhZQlJjS/ZAdwjaQOLJoDiuqV0BsD4nFX+eyT2CUnYUkNQtJ+ywk 7chqFjCyrGIUTS1ILihOSq8w0itOzC0uzUvXS87P3cQITkLPFu1g/Hfe+hCjAAejEg+vxE2h MCHWxLLiytxDjBIczEoivD+5hMOEeFMSK6tSi/Lji0pzUosPMZoCY20is5Rocj4wQeaVxBsa m5ibGptaGBiam5spifPe2MsQJiSQnliSmp2aWpBaBNPHxMEp1cC4oqvuStw9USfT1yXvYyVr 8q1OliZeUU+Mcj1+MoTp/76O78eOJuWkua+RCPijfan0kOetice5NwqfW3b1l6XPrIgF3/6X VJyIb12SVm84eXdm5pt3P+I+G1/1czzzRk5//p8j7nf2zry/51tloe0up7PcV2bNvzJ36a7b +wLkBFYLtfIx7aozU2Ipzkg01GIuKk4EAD5BmghYAwAA DLP-Filter: Pass X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t9683Pmc012892 Hello Will Here is the version 3 of the patch correcting earlier issues. v2 -> v3 : Removed the comment related to Qspinlock, changed !defined to #ifndef. v1 -> v2 : Extended the guard code to cover the byte exchange case as well following opinion of Will Deacon. Checkpatch has been run and issues were taken care of. Since support for half-word atomic exchange was not there and Qspinlock on ARM requires it, modified __xchg() to add support for that as well. ARMv6 and lower does not support ldrex{b,h} so, added a guard code to prevent build breaks. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 916a274..c6436c1 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size switch (size) { #if __LINUX_ARM_ARCH__ >= 6 +#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */ case 1: asm volatile("@ __xchg1\n" "1: ldrexb %0, [%3]\n" @@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; + case 2: + asm volatile("@ __xchg2\n" + "1: ldrexh %0, [%3]\n" + " strexh %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4\n" "1: ldrex %0, [%3]\n" -- 1.9.1 ------- Original Message ------- Sender : Sarbojit Ganguly Technical Lead/SRI-Bangalore-AP Systems 1/Samsung Electronics Date : Oct 06, 2015 08:38 (GMT+05:30) Title : Re: Re: Re: [PATCH v2] arm: Adding support for atomic half word exchange Hello Will, Thank you so much for the review. I have thought it over and it makes sense not to have that comment in cmpxchg.h, I will also change !defined to #ifndef and quickly post a v3. Regards, Sarbojit ------- Original Message ------- Sender : Will Deacon Date : Oct 05, 2015 21:30 (GMT+05:30) Title : Re: Re: [PATCH v2] arm: Adding support for atomic half word exchange On Mon, Oct 05, 2015 at 01:10:53PM +0000, Sarbojit Ganguly wrote: > My sincere apologies for the format issue. This was due to the e-mail editor > which reformats the text. > I am reposting the patch, please let me know if it is ok this time. > > > v1-->v2 : Extended the guard code to cover the byte exchange case as > well following opinion of Will Deacon. > Checkpatch has been run and issues were taken care of. > > Since support for half-word atomic exchange was not there and Qspinlock > on ARM requires it, modified __xchg() to add support for that as well. > ARMv6 and lower does not support ldrex{b,h} so, added a guard code > to prevent build breaks. > > Signed-off-by: Sarbojit Ganguly > --- > arch/arm/include/asm/cmpxchg.h | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h > index 916a274..a53cbeb 100644 > --- a/arch/arm/include/asm/cmpxchg.h > +++ b/arch/arm/include/asm/cmpxchg.h > @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size > > switch (size) { > #if __LINUX_ARM_ARCH__ >= 6 > +#if !defined(CONFIG_CPU_V6) #ifndef ? (to match the __cmpxchg code). > case 1: > asm volatile("@ __xchg1\n" > "1: ldrexb %0, [%3]\n" > @@ -49,6 +50,22 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size > : "r" (x), "r" (ptr) > : "memory", "cc"); > break; > + > + /* > + * Half-word atomic exchange, required > + * for Qspinlock support on ARM. > + */ I think I said it before, but I don't think this comment is of any real value. Other than those, this looks ok to me. Will{.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I