[PATCH 0/7] HWMOD fixes for AM33xx PWM submodules and device tree nodes.

[PATCH 0/7] HWMOD fixes for AM33xx PWM submodules and device tree nodes.

[Philip Avinash]

This patch series is being part of [1] and resubmitting on top of 3.8-rc1 to
make it to 3.9.

In AM33xx PWM sub modules like ECAP, EHRPWM & EQEP are  integrated to
PWM subsystem. All these submodules shares the resources (clock) & has
a clock gating register in PWM Subsystem. So a parent PWM subsystem
driver is created. To support PWM subsystem driver, parent child
relation is created in HWMOD entry in patch #2.

In addition EHRPWM module requires explicit clock gating from control
module. Hence add clock node for tbclk handling in patch #4.

Patch #3 to support common clock migration for AM33xx.

Also Device tree nodes populated to support parent child relation
between PWMSS, ECAP & EHRPWM submodules (patch #5, 6 & 7).

This patch series based on linux_omap/master [2] and tested for
backlight with ECAP on AM335x-evm & AM335x-evmsk.

1. https://lkml.org/lkml/2012/11/27/120
2. http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap.git;a=commit;h=c4e2e79ff7c9f4fdad7da432c6b449121cc3033e

Philip Avinash (7):
  ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries
  ARM: OMAP: AM33xx hwmod: Add parent-child relationship for PWM
    subsystem
  pwm: pwm-tiehrpwm: Update the clock handling of pwm-tiehrpwm driver
  ARM: AM33XX: clk: Add clock node for EHRPWM TBCLK
  ARM: dts: AM33XX: Add PWMSS device tree nodes
  ARM: dts: AM33XX: Add PWM backlight DT data to  am335x-evm
  ARM: dts: AM33XX: Add PWM backlight DT data to am335x-evmsk

 arch/arm/boot/dts/am335x-evm.dts           |   23 ++
 arch/arm/boot/dts/am335x-evmsk.dts         |   23 ++
 arch/arm/boot/dts/am33xx.dtsi              |   84 ++++++
 arch/arm/mach-omap2/cclock33xx_data.c      |   30 +++
 arch/arm/mach-omap2/control.h              |    8 +
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c |  390 ++++++++++++++++++----------
 drivers/pwm/pwm-tiehrpwm.c                 |    4 +-
 7 files changed, 417 insertions(+), 145 deletions(-)

-- 
1.7.9.5

[PATCH 1/7] ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries

[Philip Avinash]

EQEP entry is HWMOD entry is not present in HWMOD entry. Also address
ranges specified for EACP & EHRPWM is not correct & HWMOD flags of
ADDR_TYPE_RT is added to PWM subsystem register address space. This
patch
1. Corrects register address mapping for ECAP & EHRPWM
2. Removes  HWMOD flags in PWM submodule register address space.
3. Adds EQEP HWMOD entries.

Signed-off-by: Philip Avinash <avinashphilip@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c |  158 +++++++++++++++++++++++++---
 1 file changed, 145 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 081c71e..42a841b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -784,7 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
 };
 
 /*
- * 'epwmss' class: ecap0,1,2,  ehrpwm0,1,2
+ * 'epwmss' class: ehrpwm0,1,2 eqep0,1,2 ecap0,1,2
  */
 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 	.rev_offs	= 0x0,
@@ -864,6 +864,66 @@ static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
 	},
 };
 
+/* eqep0 */
+static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
+	{ .irq = 79 + OMAP_INTC_START, },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_eqep0_hwmod = {
+	.name		= "eqep0",
+	.class		= &am33xx_epwmss_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
+	.mpu_irqs	= am33xx_eqep0_irqs,
+	.main_clk	= "l4ls_gclk",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* eqep1 */
+static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
+	{ .irq = 88 + OMAP_INTC_START, },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_eqep1_hwmod = {
+	.name		= "eqep1",
+	.class		= &am33xx_epwmss_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
+	.mpu_irqs	= am33xx_eqep1_irqs,
+	.main_clk	= "l4ls_gclk",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* eqep2 */
+static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
+	{ .irq = 89 + OMAP_INTC_START, },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_eqep2_hwmod = {
+	.name		= "eqep2",
+	.class		= &am33xx_epwmss_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
+	.mpu_irqs	= am33xx_eqep2_irqs,
+	.main_clk	= "l4ls_gclk",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
 /* ecap0 */
 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
 	{ .irq = 31 + OMAP_INTC_START, },
@@ -2559,8 +2619,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48300200,
-		.pa_end		= 0x48300200 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48300200 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -2585,8 +2644,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48302200,
-		.pa_end		= 0x48302200 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48302200 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -2611,8 +2669,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48304200,
-		.pa_end		= 0x48304200 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48304200 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -2629,6 +2686,81 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
  * Splitting the resources to handle access of PWMSS config space
  * and module specific part independently
  */
+static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
+	{
+		.pa_start	= 0x48300000,
+		.pa_end		= 0x48300000 + SZ_16 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{
+		.pa_start	= 0x48300180,
+		.pa_end		= 0x48300180 + SZ_128 - 1,
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep0 = {
+	.master		= &am33xx_l4_ls_hwmod,
+	.slave		= &am33xx_eqep0_hwmod,
+	.clk		= "l4ls_gclk",
+	.addr		= am33xx_eqep0_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
+	{
+		.pa_start	= 0x48302000,
+		.pa_end		= 0x48302000 + SZ_16 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{
+		.pa_start	= 0x48302180,
+		.pa_end		= 0x48302180 + SZ_128 - 1,
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep1 = {
+	.master		= &am33xx_l4_ls_hwmod,
+	.slave		= &am33xx_eqep1_hwmod,
+	.clk		= "l4ls_gclk",
+	.addr		= am33xx_eqep1_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
+	{
+		.pa_start	= 0x48304000,
+		.pa_end		= 0x48304000 + SZ_16 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{
+		.pa_start	= 0x48304180,
+		.pa_end		= 0x48304180 + SZ_128 - 1,
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep2 = {
+	.master		= &am33xx_l4_ls_hwmod,
+	.slave		= &am33xx_eqep2_hwmod,
+	.clk		= "l4ls_gclk",
+	.addr		= am33xx_eqep2_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
 static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
 	{
 		.pa_start	= 0x48300000,
@@ -2637,8 +2769,7 @@ static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48300100,
-		.pa_end		= 0x48300100 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48300100 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -2663,8 +2794,7 @@ static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48302100,
-		.pa_end		= 0x48302100 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48302100 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -2689,8 +2819,7 @@ static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48304100,
-		.pa_end		= 0x48304100 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48304100 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -3388,6 +3517,9 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l4_ls__ehrpwm0,
 	&am33xx_l4_ls__ehrpwm1,
 	&am33xx_l4_ls__ehrpwm2,
+	&am33xx_l4_ls__eqep0,
+	&am33xx_l4_ls__eqep1,
+	&am33xx_l4_ls__eqep2,
 	&am33xx_l4_ls__ecap0,
 	&am33xx_l4_ls__ecap1,
 	&am33xx_l4_ls__ecap2,
-- 
1.7.9.5

[PATCH 2/7] ARM: OMAP: AM33xx hwmod: Add parent-child relationship for PWM subsystem

[Philip Avinash]

As part of PWM subsystem integration, PWM subsystem are sharing
resources like clock across submodules (ECAP, EQEP & EHRPWM). To handle
resource sharing & IP integration  rework on parent child relation
between PWMSS and ECAP, EQEP & EHRPWM child devices to support runtime PM.

Signed-off-by: Philip Avinash <avinashphilip@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c |  434 +++++++++++++---------------
 1 file changed, 203 insertions(+), 231 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 42a841b..5e59320 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -783,9 +783,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
 	},
 };
 
-/*
- * 'epwmss' class: ehrpwm0,1,2 eqep0,1,2 ecap0,1,2
- */
+/* pwmss  */
 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 	.rev_offs	= 0x0,
 	.sysc_offs	= 0x4,
@@ -801,67 +799,44 @@ static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 	.sysc		= &am33xx_epwmss_sysc,
 };
 
-/* ehrpwm0 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
-	{ .name = "int", .irq = 86 + OMAP_INTC_START, },
-	{ .name = "tzint", .irq = 58 + OMAP_INTC_START, },
-	{ .irq = -1 },
+static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
+	.name		= "ecap",
 };
 
-static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
-	.name		= "ehrpwm0",
-	.class		= &am33xx_epwmss_hwmod_class,
-	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ehrpwm0_irqs,
-	.main_clk	= "l4ls_gclk",
-	.prcm		= {
-		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
-			.modulemode	= MODULEMODE_SWCTRL,
-		},
-	},
+static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
+	.name		= "eqep",
 };
 
-/* ehrpwm1 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
-	{ .name = "int", .irq = 87 + OMAP_INTC_START, },
-	{ .name = "tzint", .irq = 59 + OMAP_INTC_START, },
-	{ .irq = -1 },
+static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
+	.name		= "ehrpwm",
 };
 
-static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
-	.name		= "ehrpwm1",
+/* epwmss0 */
+static struct omap_hwmod am33xx_epwmss0_hwmod = {
+	.name		= "epwmss0",
 	.class		= &am33xx_epwmss_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ehrpwm1_irqs,
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
 };
 
-/* ehrpwm2 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
-	{ .name = "int", .irq = 39 + OMAP_INTC_START, },
-	{ .name = "tzint", .irq = 60 + OMAP_INTC_START, },
+/* ecap0 */
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+	{ .irq = 31 + OMAP_INTC_START, },
 	{ .irq = -1 },
 };
 
-static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
-	.name		= "ehrpwm2",
-	.class		= &am33xx_epwmss_hwmod_class,
+static struct omap_hwmod am33xx_ecap0_hwmod = {
+	.name		= "ecap0",
+	.class		= &am33xx_ecap_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ehrpwm2_irqs,
+	.mpu_irqs	= am33xx_ecap0_irqs,
 	.main_clk	= "l4ls_gclk",
-	.prcm		= {
-		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
-			.modulemode	= MODULEMODE_SWCTRL,
-		},
-	},
 };
 
 /* eqep0 */
@@ -872,29 +847,32 @@ static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
 
 static struct omap_hwmod am33xx_eqep0_hwmod = {
 	.name		= "eqep0",
-	.class		= &am33xx_epwmss_hwmod_class,
+	.class		= &am33xx_eqep_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
 	.mpu_irqs	= am33xx_eqep0_irqs,
 	.main_clk	= "l4ls_gclk",
-	.prcm		= {
-		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
-			.modulemode	= MODULEMODE_SWCTRL,
-		},
-	},
 };
 
-/* eqep1 */
-static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
-	{ .irq = 88 + OMAP_INTC_START, },
+/* ehrpwm0 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
+	{ .name = "int", .irq = 86 + OMAP_INTC_START, },
+	{ .name = "tzint", .irq = 58 + OMAP_INTC_START, },
 	{ .irq = -1 },
 };
 
-static struct omap_hwmod am33xx_eqep1_hwmod = {
-	.name		= "eqep1",
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+	.name		= "ehrpwm0",
+	.class		= &am33xx_ehrpwm_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
+	.mpu_irqs	= am33xx_ehrpwm0_irqs,
+	.main_clk	= "l4ls_gclk",
+};
+
+/* epwmss1 */
+static struct omap_hwmod am33xx_epwmss1_hwmod = {
+	.name		= "epwmss1",
 	.class		= &am33xx_epwmss_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_eqep1_irqs,
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
@@ -904,61 +882,58 @@ static struct omap_hwmod am33xx_eqep1_hwmod = {
 	},
 };
 
-/* eqep2 */
-static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
-	{ .irq = 89 + OMAP_INTC_START, },
+/* ecap1 */
+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
+	{ .irq = 47 + OMAP_INTC_START, },
 	{ .irq = -1 },
 };
 
-static struct omap_hwmod am33xx_eqep2_hwmod = {
-	.name		= "eqep2",
-	.class		= &am33xx_epwmss_hwmod_class,
+static struct omap_hwmod am33xx_ecap1_hwmod = {
+	.name		= "ecap1",
+	.class		= &am33xx_ecap_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_eqep2_irqs,
+	.mpu_irqs	= am33xx_ecap1_irqs,
 	.main_clk	= "l4ls_gclk",
-	.prcm		= {
-		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
-			.modulemode	= MODULEMODE_SWCTRL,
-		},
-	},
 };
 
-/* ecap0 */
-static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
-	{ .irq = 31 + OMAP_INTC_START, },
+/* eqep1 */
+static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
+	{ .irq = 88 + OMAP_INTC_START, },
 	{ .irq = -1 },
 };
 
-static struct omap_hwmod am33xx_ecap0_hwmod = {
-	.name		= "ecap0",
-	.class		= &am33xx_epwmss_hwmod_class,
+static struct omap_hwmod am33xx_eqep1_hwmod = {
+	.name		= "eqep1",
+	.class		= &am33xx_eqep_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ecap0_irqs,
+	.mpu_irqs	= am33xx_eqep1_irqs,
 	.main_clk	= "l4ls_gclk",
-	.prcm		= {
-		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
-			.modulemode	= MODULEMODE_SWCTRL,
-		},
-	},
 };
 
-/* ecap1 */
-static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
-	{ .irq = 47 + OMAP_INTC_START, },
+/* ehrpwm1 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+	{ .name = "int", .irq = 87 + OMAP_INTC_START, },
+	{ .name = "tzint", .irq = 59 + OMAP_INTC_START, },
 	{ .irq = -1 },
 };
 
-static struct omap_hwmod am33xx_ecap1_hwmod = {
-	.name		= "ecap1",
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+	.name		= "ehrpwm1",
+	.class		= &am33xx_ehrpwm_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
+	.mpu_irqs	= am33xx_ehrpwm1_irqs,
+	.main_clk	= "l4ls_gclk",
+};
+
+/* epwmss2 */
+static struct omap_hwmod am33xx_epwmss2_hwmod = {
+	.name		= "epwmss2",
 	.class		= &am33xx_epwmss_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
-	.mpu_irqs	= am33xx_ecap1_irqs,
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
@@ -972,16 +947,39 @@ static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
 
 static struct omap_hwmod am33xx_ecap2_hwmod = {
 	.name		= "ecap2",
+	.class		= &am33xx_ecap_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
 	.mpu_irqs	= am33xx_ecap2_irqs,
-	.class		= &am33xx_epwmss_hwmod_class,
+	.main_clk	= "l4ls_gclk",
+};
+
+/* eqep2 */
+static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
+	{ .irq = 89 + OMAP_INTC_START, },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_eqep2_hwmod = {
+	.name		= "eqep2",
+	.class		= &am33xx_eqep_hwmod_class,
 	.clkdm_name	= "l4ls_clkdm",
+	.mpu_irqs	= am33xx_eqep2_irqs,
+	.main_clk	= "l4ls_gclk",
+};
+
+/* ehrpwm2 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+	{ .name = "int", .irq = 39 + OMAP_INTC_START, },
+	{ .name = "tzint", .irq = 60 + OMAP_INTC_START, },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+	.name		= "ehrpwm2",
+	.class		= &am33xx_ehrpwm_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
+	.mpu_irqs	= am33xx_ehrpwm2_irqs,
 	.main_clk	= "l4ls_gclk",
-	.prcm		= {
-		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
-			.modulemode	= MODULEMODE_SWCTRL,
-		},
-	},
 };
 
 /*
@@ -2607,116 +2605,106 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
 	.user		= OCP_USER_MPU,
 };
 
-/*
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
+static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
 	{
 		.pa_start	= 0x48300000,
 		.pa_end		= 0x48300000 + SZ_16 - 1,
 		.flags		= ADDR_TYPE_RT
 	},
-	{
-		.pa_start	= 0x48300200,
-		.pa_end		= 0x48300200 + SZ_128 - 1,
-	},
 	{ }
 };
 
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
+static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
 	.master		= &am33xx_l4_ls_hwmod,
-	.slave		= &am33xx_ehrpwm0_hwmod,
+	.slave		= &am33xx_epwmss0_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ehrpwm0_addr_space,
+	.addr		= am33xx_epwmss0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-/*
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
-	{
-		.pa_start	= 0x48302000,
-		.pa_end		= 0x48302000 + SZ_16 - 1,
-		.flags		= ADDR_TYPE_RT
-	},
+static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
 	{
-		.pa_start	= 0x48302200,
-		.pa_end		= 0x48302200 + SZ_128 - 1,
+		.pa_start	= 0x48300100,
+		.pa_end		= 0x48300100 + SZ_128 - 1,
 	},
 	{ }
 };
 
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
-	.master		= &am33xx_l4_ls_hwmod,
-	.slave		= &am33xx_ehrpwm1_hwmod,
+static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
+	.master		= &am33xx_epwmss0_hwmod,
+	.slave		= &am33xx_ecap0_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ehrpwm1_addr_space,
+	.addr		= am33xx_ecap0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-/*
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
 	{
-		.pa_start	= 0x48304000,
-		.pa_end		= 0x48304000 + SZ_16 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_start	= 0x48300180,
+		.pa_end		= 0x48300180 + SZ_128 - 1,
 	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
+	.master		= &am33xx_epwmss0_hwmod,
+	.slave		= &am33xx_eqep0_hwmod,
+	.clk		= "l4ls_gclk",
+	.addr		= am33xx_eqep0_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
 	{
-		.pa_start	= 0x48304200,
-		.pa_end		= 0x48304200 + SZ_128 - 1,
+		.pa_start	= 0x48300200,
+		.pa_end		= 0x48300200 + SZ_128 - 1,
 	},
 	{ }
 };
 
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
-	.master		= &am33xx_l4_ls_hwmod,
-	.slave		= &am33xx_ehrpwm2_hwmod,
+static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
+	.master		= &am33xx_epwmss0_hwmod,
+	.slave		= &am33xx_ehrpwm0_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ehrpwm2_addr_space,
+	.addr		= am33xx_ehrpwm0_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-/*
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
+
+static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
 	{
-		.pa_start	= 0x48300000,
-		.pa_end		= 0x48300000 + SZ_16 - 1,
+		.pa_start	= 0x48302000,
+		.pa_end		= 0x48302000 + SZ_16 - 1,
 		.flags		= ADDR_TYPE_RT
 	},
-	{
-		.pa_start	= 0x48300180,
-		.pa_end		= 0x48300180 + SZ_128 - 1,
-	},
 	{ }
 };
 
-static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep0 = {
+static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
 	.master		= &am33xx_l4_ls_hwmod,
-	.slave		= &am33xx_eqep0_hwmod,
+	.slave		= &am33xx_epwmss1_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_eqep0_addr_space,
+	.addr		= am33xx_epwmss1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-/*
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
+static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
 	{
-		.pa_start	= 0x48302000,
-		.pa_end		= 0x48302000 + SZ_16 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_start	= 0x48302100,
+		.pa_end		= 0x48302100 + SZ_128 - 1,
 	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
+	.master		= &am33xx_epwmss1_hwmod,
+	.slave		= &am33xx_ecap1_hwmod,
+	.clk		= "l4ls_gclk",
+	.addr		= am33xx_ecap1_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
 	{
 		.pa_start	= 0x48302180,
 		.pa_end		= 0x48302180 + SZ_128 - 1,
@@ -2724,111 +2712,92 @@ static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
 	{ }
 };
 
-static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep1 = {
-	.master		= &am33xx_l4_ls_hwmod,
+static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
+	.master		= &am33xx_epwmss1_hwmod,
 	.slave		= &am33xx_eqep1_hwmod,
 	.clk		= "l4ls_gclk",
 	.addr		= am33xx_eqep1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-/*
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
-	{
-		.pa_start	= 0x48304000,
-		.pa_end		= 0x48304000 + SZ_16 - 1,
-		.flags		= ADDR_TYPE_RT
-	},
+static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
 	{
-		.pa_start	= 0x48304180,
-		.pa_end		= 0x48304180 + SZ_128 - 1,
+		.pa_start	= 0x48302200,
+		.pa_end		= 0x48302200 + SZ_128 - 1,
 	},
 	{ }
 };
 
-static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep2 = {
-	.master		= &am33xx_l4_ls_hwmod,
-	.slave		= &am33xx_eqep2_hwmod,
+static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
+	.master		= &am33xx_epwmss1_hwmod,
+	.slave		= &am33xx_ehrpwm1_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_eqep2_addr_space,
+	.addr		= am33xx_ehrpwm1_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-/*
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
+static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
 	{
-		.pa_start	= 0x48300000,
-		.pa_end		= 0x48300000 + SZ_16 - 1,
+		.pa_start	= 0x48304000,
+		.pa_end		= 0x48304000 + SZ_16 - 1,
 		.flags		= ADDR_TYPE_RT
 	},
-	{
-		.pa_start	= 0x48300100,
-		.pa_end		= 0x48300100 + SZ_128 - 1,
-	},
 	{ }
 };
 
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
+static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
 	.master		= &am33xx_l4_ls_hwmod,
-	.slave		= &am33xx_ecap0_hwmod,
+	.slave		= &am33xx_epwmss2_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ecap0_addr_space,
+	.addr		= am33xx_epwmss2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-/*
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
-	{
-		.pa_start	= 0x48302000,
-		.pa_end		= 0x48302000 + SZ_16 - 1,
-		.flags		= ADDR_TYPE_RT
-	},
+static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
 	{
-		.pa_start	= 0x48302100,
-		.pa_end		= 0x48302100 + SZ_128 - 1,
+		.pa_start	= 0x48304100,
+		.pa_end		= 0x48304100 + SZ_128 - 1,
 	},
 	{ }
 };
 
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
-	.master		= &am33xx_l4_ls_hwmod,
-	.slave		= &am33xx_ecap1_hwmod,
+static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
+	.master		= &am33xx_epwmss2_hwmod,
+	.slave		= &am33xx_ecap2_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ecap1_addr_space,
+	.addr		= am33xx_ecap2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
-/*
- * Splitting the resources to handle access of PWMSS config space
- * and module specific part independently
- */
-static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
 	{
-		.pa_start	= 0x48304000,
-		.pa_end		= 0x48304000 + SZ_16 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_start	= 0x48304180,
+		.pa_end		= 0x48304180 + SZ_128 - 1,
 	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
+	.master		= &am33xx_epwmss2_hwmod,
+	.slave		= &am33xx_eqep2_hwmod,
+	.clk		= "l4ls_gclk",
+	.addr		= am33xx_eqep2_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
 	{
-		.pa_start	= 0x48304100,
-		.pa_end		= 0x48304100 + SZ_128 - 1,
+		.pa_start	= 0x48304200,
+		.pa_end		= 0x48304200 + SZ_128 - 1,
 	},
 	{ }
 };
 
-static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
-	.master		= &am33xx_l4_ls_hwmod,
-	.slave		= &am33xx_ecap2_hwmod,
+static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
+	.master		= &am33xx_epwmss2_hwmod,
+	.slave		= &am33xx_ehrpwm2_hwmod,
 	.clk		= "l4ls_gclk",
-	.addr		= am33xx_ecap2_addr_space,
+	.addr		= am33xx_ehrpwm2_addr_space,
 	.user		= OCP_USER_MPU,
 };
 
@@ -3514,15 +3483,18 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l4_ls__uart6,
 	&am33xx_l4_ls__spinlock,
 	&am33xx_l4_ls__elm,
-	&am33xx_l4_ls__ehrpwm0,
-	&am33xx_l4_ls__ehrpwm1,
-	&am33xx_l4_ls__ehrpwm2,
-	&am33xx_l4_ls__eqep0,
-	&am33xx_l4_ls__eqep1,
-	&am33xx_l4_ls__eqep2,
-	&am33xx_l4_ls__ecap0,
-	&am33xx_l4_ls__ecap1,
-	&am33xx_l4_ls__ecap2,
+	&am33xx_l4_ls__epwmss0,
+	&am33xx_epwmss0__ecap0,
+	&am33xx_epwmss0__eqep0,
+	&am33xx_epwmss0__ehrpwm0,
+	&am33xx_l4_ls__epwmss1,
+	&am33xx_epwmss1__ecap1,
+	&am33xx_epwmss1__eqep1,
+	&am33xx_epwmss1__ehrpwm1,
+	&am33xx_l4_ls__epwmss2,
+	&am33xx_epwmss2__ecap2,
+	&am33xx_epwmss2__eqep2,
+	&am33xx_epwmss2__ehrpwm2,
 	&am33xx_l3_s__gpmc,
 	&am33xx_l3_main__lcdc,
 	&am33xx_l4_ls__mcspi0,
-- 
1.7.9.5

[PATCH 3/7] pwm: pwm-tiehrpwm: Update the clock handling of pwm-tiehrpwm driver

[Philip Avinash]

The clock framework has changed and it's now better to invoke
clock_prepare_enable() and clk_disable_unprepare() rather than the
legacy clk_enable() and clk_disable() calls. This patch converts the
pwm-tiehrpwm driver to the new framework.

Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
---
In 3.8-rc1, common clock frame work support added to AM335x.

 drivers/pwm/pwm-tiehrpwm.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index 72a6dd4..af6f162 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -341,7 +341,7 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 	configure_polarity(pc, pwm->hwpwm);
 
 	/* Enable TBCLK before enabling PWM device */
-	clk_enable(pc->tbclk);
+	clk_prepare_enable(pc->tbclk);
 
 	/* Enable time counter for free_run */
 	ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN);
@@ -372,7 +372,7 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 	ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
 
 	/* Disabling TBCLK on PWM disable */
-	clk_disable(pc->tbclk);
+	clk_disable_unprepare(pc->tbclk);
 
 	/* Stop Time base counter */
 	ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT);
-- 
1.7.9.5

[PATCH 4/7] ARM: AM33XX: clk: Add clock node for EHRPWM TBCLK

[Philip Avinash]

EHRPWM module requires explicit clock gating of TBCLK from control
module. Hence add TBCLK clock node in clock tree for EHRPWM modules.

Signed-off-by: Philip Avinash <avinashphilip@ti.com>
---
- common clock frame work support

 arch/arm/mach-omap2/cclock33xx_data.c |   30 ++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/control.h         |    8 ++++++++
 2 files changed, 38 insertions(+)

diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ea64ad6..7ff9bc9 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -832,6 +832,33 @@ static struct clk_hw_omap wdt1_fck_hw = {
 
 DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
 
+static const char *pwmss_clk_parents[] = {
+	"dpll_per_m2_ck",
+};
+
+static const struct clk_ops ehrpwm_tbclk_ops = {
+	.enable		= &omap2_dflt_clk_enable,
+	.disable	= &omap2_dflt_clk_disable,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
+			 0, NULL, 0,
+			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+			 AM33XX_PWMSS0_TBCLKEN_SHIFT,
+			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
+			 0, NULL, 0,
+			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+			 AM33XX_PWMSS1_TBCLKEN_SHIFT,
+			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
+			 0, NULL, 0,
+			 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+			 AM33XX_PWMSS2_TBCLKEN_SHIFT,
+			 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
 /*
  * clkdev
  */
@@ -910,6 +937,9 @@ static struct omap_clk am33xx_clks[] = {
 	CLK(NULL,	"clkout2_div_ck",	&clkout2_div_ck,	CK_AM33XX),
 	CLK(NULL,	"timer_32k_ck",		&clkdiv32k_ick,	CK_AM33XX),
 	CLK(NULL,	"timer_sys_ck",		&sys_clkin_ck,	CK_AM33XX),
+	CLK("48300200.ehrpwm",	"tbclk",	&ehrpwm0_tbclk,	CK_AM33XX),
+	CLK("48302200.ehrpwm",	"tbclk",	&ehrpwm1_tbclk,	CK_AM33XX),
+	CLK("48304200.ehrpwm",	"tbclk",	&ehrpwm2_tbclk,	CK_AM33XX),
 };
 
 
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 3d944d3..ad4f1d8 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -358,6 +358,14 @@
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH		0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK		(0x3 << 22)
 
+/* AM33XX PWMSS Control register */
+#define AM33XX_PWMSS_TBCLK_CLKCTRL			0x664
+
+/* AM33XX  PWMSS Control bitfields */
+#define AM33XX_PWMSS0_TBCLKEN_SHIFT			0
+#define AM33XX_PWMSS1_TBCLKEN_SHIFT			1
+#define AM33XX_PWMSS2_TBCLKEN_SHIFT			2
+
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
 #define OMAP3_CONTROL_OMAP_STATUS	0x044c
 
-- 
1.7.9.5

[PATCH 5/7] ARM: dts: AM33XX: Add PWMSS device tree nodes

[Philip Avinash]

Add PWMSS device tree nodes in relation with ECAP & EHRPWM DT nodes to
AM33XX SoC family. Also populates device tree nodes for ECAP & EHRPWM by
adding necessary properties like pwm-cells, base reg & set disabled as
status.

Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
---
 arch/arm/boot/dts/am33xx.dtsi |   84 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index c2f14e8..6aa51cb 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -385,5 +385,89 @@
 				mac-address = [ 00 00 00 00 00 00 ];
 			};
 		};
+
+		epwmss0: epwmss@48300000 {
+			compatible = "ti,am33xx-pwmss";
+			reg = <0x48300000 0x10>;
+			ti,hwmods = "epwmss0";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+			ranges = <0x48300100 0x48300100 0x80   /* ECAP */
+				  0x48300180 0x48300180 0x80   /* EQEP */
+				  0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+			ecap0: ecap@48300100 {
+				compatible = "ti,am33xx-ecap";
+				#pwm-cells = <3>;
+				reg = <0x48300100 0x80>;
+				ti,hwmods = "ecap0";
+				status = "disabled";
+			};
+
+			ehrpwm0: ehrpwm@48300200 {
+				compatible = "ti,am33xx-ehrpwm";
+				#pwm-cells = <3>;
+				reg = <0x48300200 0x80>;
+				ti,hwmods = "ehrpwm0";
+				status = "disabled";
+			};
+		};
+
+		epwmss1: epwmss@48302000 {
+			compatible = "ti,am33xx-pwmss";
+			reg = <0x48302000 0x10>;
+			ti,hwmods = "epwmss1";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+			ranges = <0x48302100 0x48302100 0x80   /* ECAP */
+				  0x48302180 0x48302180 0x80   /* EQEP */
+				  0x48302200 0x48302200 0x80>; /* EHRPWM */
+
+			ecap1: ecap@48302100 {
+				compatible = "ti,am33xx-ecap";
+				#pwm-cells = <3>;
+				reg = <0x48302100 0x80>;
+				ti,hwmods = "ecap1";
+				status = "disabled";
+			};
+
+			ehrpwm1: ehrpwm@48302200 {
+				compatible = "ti,am33xx-ehrpwm";
+				#pwm-cells = <3>;
+				reg = <0x48302200 0x80>;
+				ti,hwmods = "ehrpwm1";
+				status = "disabled";
+			};
+		};
+
+		epwmss2: epwmss@48304000 {
+			compatible = "ti,am33xx-pwmss";
+			reg = <0x48304000 0x10>;
+			ti,hwmods = "epwmss2";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+			ranges = <0x48304100 0x48304100 0x80   /* ECAP */
+				  0x48304180 0x48304180 0x80   /* EQEP */
+				  0x48304200 0x48304200 0x80>; /* EHRPWM */
+
+			ecap2: ecap@48304100 {
+				compatible = "ti,am33xx-ecap";
+				#pwm-cells = <3>;
+				reg = <0x48304100 0x80>;
+				ti,hwmods = "ecap2";
+				status = "disabled";
+			};
+
+			ehrpwm2: ehrpwm@48304200 {
+				compatible = "ti,am33xx-ehrpwm";
+				#pwm-cells = <3>;
+				reg = <0x48304200 0x80>;
+				ti,hwmods = "ehrpwm2";
+				status = "disabled";
+			};
+		};
 	};
 };
-- 
1.7.9.5

[PATCH 6/7] ARM: dts: AM33XX: Add PWM backlight DT data to am335x-evm

[Philip Avinash]

PWM output from ecap0 uses as backlight source. Also adds low threshold
value to have a uniform divisions in brightness-levels scales.

Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
---
 arch/arm/boot/dts/am335x-evm.dts |   23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..fd3b691 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,12 @@
 				0x154 0x27	/* spi0_d0.gpio0_3, INPUT | MODE7 */
 			>;
 		};
+
+		ecap0_pins: backlight_pins {
+			pinctrl-single,pins = <
+				0x164 0x0	/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+			>;
+		};
 	};
 
 	ocp {
@@ -102,6 +108,16 @@
 				reg = <0x48>;
 			};
 		};
+
+		epwmss0: epwmss@48300000 {
+			status = "okay";
+
+			ecap0: ecap@48300100 {
+				status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <&ecap0_pins>;
+			};
+		};
 	};
 
 	vbat: fixedregulator@0 {
@@ -158,6 +174,13 @@
 			gpio-key,wakeup;
 		};
 	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&ecap0 0 50000 0>;
+		brightness-levels = <0 51 53 56 62 75 101 152 255>;
+		default-brightness-level = <8>;
+	};
 };
 
 /include/ "tps65910.dtsi"
-- 
1.7.9.5

[PATCH 7/7] ARM: dts: AM33XX: Add PWM backlight DT data to am335x-evmsk

[Philip Avinash]

PWM output from ecap2 uses as backlight source. Also adds low threshold
value to have a uniform divisions in brightness-levels scales with
inverse polarity.

Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
---
 arch/arm/boot/dts/am335x-evmsk.dts |   23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162..a50f286 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,12 @@
 				0x9c 0x27	/* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */
 			>;
 		};
+
+		ecap2_pins: backlight_pins {
+			pinctrl-single,pins = <
+				0x19c 0x4	/* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
+			>;
+		};
 	};
 
 	ocp {
@@ -94,6 +100,16 @@
 				st,max-limit-z = <750>;
 			};
 		};
+
+		epwmss2: epwmss@48304000 {
+			status = "okay";
+
+			ecap2: ecap@48304100 {
+				status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <&ecap2_pins>;
+			};
+		};
 	};
 
 	vbat: fixedregulator@0 {
@@ -170,6 +186,13 @@
 			gpios = <&gpio3 5 0>;
 		};
 	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&ecap2 0 50000 1>;
+		brightness-levels = <0 58 61 66 75 90 125 170 255>;
+		default-brightness-level = <8>;
+	};
 };
 
 /include/ "tps65910.dtsi"
-- 
1.7.9.5

Re: [PATCH 3/7] pwm: pwm-tiehrpwm: Update the clock handling of pwm-tiehrpwm driver

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1227 bytes --]

On Wed, Jan 02, 2013 at 06:54:50PM +0530, Philip Avinash wrote:
> The clock framework has changed and it's now better to invoke
> clock_prepare_enable() and clk_disable_unprepare() rather than the
> legacy clk_enable() and clk_disable() calls. This patch converts the
> pwm-tiehrpwm driver to the new framework.
> 
> Signed-off-by: Philip Avinash <avinashphilip@ti.com>
> Cc: Thierry Reding <thierry.reding@avionic-design.de>
> ---
> In 3.8-rc1, common clock frame work support added to AM335x.
> 
>  drivers/pwm/pwm-tiehrpwm.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
> index 72a6dd4..af6f162 100644
> --- a/drivers/pwm/pwm-tiehrpwm.c
> +++ b/drivers/pwm/pwm-tiehrpwm.c
> @@ -341,7 +341,7 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>  	configure_polarity(pc, pwm->hwpwm);
>  
>  	/* Enable TBCLK before enabling PWM device */
> -	clk_enable(pc->tbclk);
> +	clk_prepare_enable(pc->tbclk);

I apparently didn't catch this before, but maybe it would be useful to
check the return value here to make sure we only proceed if the clock
can actually be enabled.

Thierry

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

RE: [PATCH 0/7] HWMOD fixes for AM33xx PWM submodules and device tree nodes.

[Philip, Avinash]

Hi Paul,

On Wed, Jan 02, 2013 at 18:54:47, Philip, Avinash wrote:
> This patch series is being part of [1] and resubmitting on top of 3.8-rc1 to
> make it to 3.9.
> 
> In AM33xx PWM sub modules like ECAP, EHRPWM & EQEP are  integrated to
> PWM subsystem. All these submodules shares the resources (clock) & has
> a clock gating register in PWM Subsystem. So a parent PWM subsystem
> driver is created. To support PWM subsystem driver, parent child
> relation is created in HWMOD entry in patch #2.
> 
> In addition EHRPWM module requires explicit clock gating from control
> module. Hence add clock node for tbclk handling in patch #4.
> 
> Patch #3 to support common clock migration for AM33xx.
> 
> Also Device tree nodes populated to support parent child relation
> between PWMSS, ECAP & EHRPWM submodules (patch #5, 6 & 7).
> 
> This patch series based on linux_omap/master [2] and tested for
> backlight with ECAP on AM335x-evm & AM335x-evmsk.

Are there any reviews on this patch series?
This patch set is required for LCD backlight work based on ECAP PWM
in am335x-evm & am335x-evmsk.

Thanks
Avinash

> 
> 1. https://lkml.org/lkml/2012/11/27/120
> 2. http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap.git;a=commit;h=c4e2e79ff7c9f4fdad7da432c6b449121cc3033e
> 
> Philip Avinash (7):
>   ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries
>   ARM: OMAP: AM33xx hwmod: Add parent-child relationship for PWM
>     subsystem
>   pwm: pwm-tiehrpwm: Update the clock handling of pwm-tiehrpwm driver
>   ARM: AM33XX: clk: Add clock node for EHRPWM TBCLK
>   ARM: dts: AM33XX: Add PWMSS device tree nodes
>   ARM: dts: AM33XX: Add PWM backlight DT data to  am335x-evm
>   ARM: dts: AM33XX: Add PWM backlight DT data to am335x-evmsk
> 
>  arch/arm/boot/dts/am335x-evm.dts           |   23 ++
>  arch/arm/boot/dts/am335x-evmsk.dts         |   23 ++
>  arch/arm/boot/dts/am33xx.dtsi              |   84 ++++++
>  arch/arm/mach-omap2/cclock33xx_data.c      |   30 +++
>  arch/arm/mach-omap2/control.h              |    8 +
>  arch/arm/mach-omap2/omap_hwmod_33xx_data.c |  390 ++++++++++++++++++----------
>  drivers/pwm/pwm-tiehrpwm.c                 |    4 +-
>  7 files changed, 417 insertions(+), 145 deletions(-)
> 
> -- 
> 1.7.9.5
> 
> 

RE: [PATCH 3/7] pwm: pwm-tiehrpwm: Update the clock handling of pwm-tiehrpwm driver

[Philip, Avinash]

On Wed, Jan 02, 2013 at 19:08:43, Thierry Reding wrote:
> On Wed, Jan 02, 2013 at 06:54:50PM +0530, Philip Avinash wrote:
> > The clock framework has changed and it's now better to invoke
> > clock_prepare_enable() and clk_disable_unprepare() rather than the
> > legacy clk_enable() and clk_disable() calls. This patch converts the
> > pwm-tiehrpwm driver to the new framework.
> > 
> > Signed-off-by: Philip Avinash <avinashphilip@ti.com>
> > Cc: Thierry Reding <thierry.reding@avionic-design.de>
> > ---
> > In 3.8-rc1, common clock frame work support added to AM335x.
> > 
> >  drivers/pwm/pwm-tiehrpwm.c |    4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
> > index 72a6dd4..af6f162 100644
> > --- a/drivers/pwm/pwm-tiehrpwm.c
> > +++ b/drivers/pwm/pwm-tiehrpwm.c
> > @@ -341,7 +341,7 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
> >  	configure_polarity(pc, pwm->hwpwm);
> >  
> >  	/* Enable TBCLK before enabling PWM device */
> > -	clk_enable(pc->tbclk);
> > +	clk_prepare_enable(pc->tbclk);
> 
> I apparently didn't catch this before, but maybe it would be useful to
> check the return value here to make sure we only proceed if the clock
> can actually be enabled.

Ok I will check return value & make it return status of pwm_enable().
I will send it as individual patch in next series. I am waiting for
reviews / acceptance of HWMOD and clock tree node patches.

Thanks
Avinash

> 
> Thierry
> 

Re: [PATCH 4/7] ARM: AM33XX: clk: Add clock node for EHRPWM TBCLK

[Paul Walmsley]

Hi,

On Wed, 2 Jan 2013, Philip Avinash wrote:

> EHRPWM module requires explicit clock gating of TBCLK from control
> module. Hence add TBCLK clock node in clock tree for EHRPWM modules.
> 
> Signed-off-by: Philip Avinash <avinashphilip@ti.com>

This patch adds some sparse[1] warnings:

> arch/arm/mach-omap2/cclock33xx_data.c:844:1: warning: Using plain 
integer as NULL pointer
> arch/arm/mach-omap2/cclock33xx_data.c:850:1: warning: Using plain 
integer as NULL pointer
> arch/arm/mach-omap2/cclock33xx_data.c:856:1: warning: Using plain 
integer as NULL pointer

Could you fix these, please?


- Paul

1. Sparse: https://sparse.wiki.kernel.org/index.php/Main_Page

Re: [PATCH 1/7] ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries

[Paul Walmsley]

Hi

On Wed, 2 Jan 2013, Philip Avinash wrote:

> EQEP entry is HWMOD entry is not present in HWMOD entry.

Patch descriptions need to make sense.  This one does not.  I've fixed it 
for you this time, but please take more care in the future.


- Paul


From: Philip Avinash <avinashphilip@ti.com>
Date: Wed, 2 Jan 2013 18:54:48 +0530
Subject: [PATCH] ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD
 entries

EQEP IP block integration data is not present in HWMOD data. Also
address ranges specified for EACP & EHRPWM are not correct & HWMOD
flags of ADDR_TYPE_RT are added to PWM subsystem register address
space. This patch:
1. Corrects register address mapping for ECAP & EHRPWM
2. Removes  HWMOD flags in PWM submodule register address space.
3. Adds EQEP HWMOD entries.

Signed-off-by: Philip Avinash <avinashphilip@ti.com>
[paul@pwsan.com: tweaked patch description]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c |  158 +++++++++++++++++++++++++---
 1 file changed, 145 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 9e34d4c..4b1cc4d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -784,7 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
 };
 
 /*
- * 'epwmss' class: ecap0,1,2,  ehrpwm0,1,2
+ * 'epwmss' class: ehrpwm0,1,2 eqep0,1,2 ecap0,1,2
  */
 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 	.rev_offs	= 0x0,
@@ -864,6 +864,66 @@ static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
 	},
 };
 
+/* eqep0 */
+static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
+	{ .irq = 79 + OMAP_INTC_START, },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_eqep0_hwmod = {
+	.name		= "eqep0",
+	.class		= &am33xx_epwmss_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
+	.mpu_irqs	= am33xx_eqep0_irqs,
+	.main_clk	= "l4ls_gclk",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* eqep1 */
+static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
+	{ .irq = 88 + OMAP_INTC_START, },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_eqep1_hwmod = {
+	.name		= "eqep1",
+	.class		= &am33xx_epwmss_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
+	.mpu_irqs	= am33xx_eqep1_irqs,
+	.main_clk	= "l4ls_gclk",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* eqep2 */
+static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
+	{ .irq = 89 + OMAP_INTC_START, },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_eqep2_hwmod = {
+	.name		= "eqep2",
+	.class		= &am33xx_epwmss_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
+	.mpu_irqs	= am33xx_eqep2_irqs,
+	.main_clk	= "l4ls_gclk",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
 /* ecap0 */
 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
 	{ .irq = 31 + OMAP_INTC_START, },
@@ -2559,8 +2619,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48300200,
-		.pa_end		= 0x48300200 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48300200 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -2585,8 +2644,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48302200,
-		.pa_end		= 0x48302200 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48302200 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -2611,8 +2669,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48304200,
-		.pa_end		= 0x48304200 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48304200 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -2629,6 +2686,81 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
  * Splitting the resources to handle access of PWMSS config space
  * and module specific part independently
  */
+static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
+	{
+		.pa_start	= 0x48300000,
+		.pa_end		= 0x48300000 + SZ_16 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{
+		.pa_start	= 0x48300180,
+		.pa_end		= 0x48300180 + SZ_128 - 1,
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep0 = {
+	.master		= &am33xx_l4_ls_hwmod,
+	.slave		= &am33xx_eqep0_hwmod,
+	.clk		= "l4ls_gclk",
+	.addr		= am33xx_eqep0_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
+	{
+		.pa_start	= 0x48302000,
+		.pa_end		= 0x48302000 + SZ_16 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{
+		.pa_start	= 0x48302180,
+		.pa_end		= 0x48302180 + SZ_128 - 1,
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep1 = {
+	.master		= &am33xx_l4_ls_hwmod,
+	.slave		= &am33xx_eqep1_hwmod,
+	.clk		= "l4ls_gclk",
+	.addr		= am33xx_eqep1_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
+	{
+		.pa_start	= 0x48304000,
+		.pa_end		= 0x48304000 + SZ_16 - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{
+		.pa_start	= 0x48304180,
+		.pa_end		= 0x48304180 + SZ_128 - 1,
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep2 = {
+	.master		= &am33xx_l4_ls_hwmod,
+	.slave		= &am33xx_eqep2_hwmod,
+	.clk		= "l4ls_gclk",
+	.addr		= am33xx_eqep2_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
 static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
 	{
 		.pa_start	= 0x48300000,
@@ -2637,8 +2769,7 @@ static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48300100,
-		.pa_end		= 0x48300100 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48300100 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -2663,8 +2794,7 @@ static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48302100,
-		.pa_end		= 0x48302100 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48302100 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -2689,8 +2819,7 @@ static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
 	},
 	{
 		.pa_start	= 0x48304100,
-		.pa_end		= 0x48304100 + SZ_256 - 1,
-		.flags		= ADDR_TYPE_RT
+		.pa_end		= 0x48304100 + SZ_128 - 1,
 	},
 	{ }
 };
@@ -3395,6 +3524,9 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l4_ls__ehrpwm0,
 	&am33xx_l4_ls__ehrpwm1,
 	&am33xx_l4_ls__ehrpwm2,
+	&am33xx_l4_ls__eqep0,
+	&am33xx_l4_ls__eqep1,
+	&am33xx_l4_ls__eqep2,
 	&am33xx_l4_ls__ecap0,
 	&am33xx_l4_ls__ecap1,
 	&am33xx_l4_ls__ecap2,
-- 
1.7.10.4

RE: [PATCH 1/7] ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries

[Hiremath, Vaibhav]

On Fri, Feb 08, 2013 at 20:40:18, Paul Walmsley wrote:
> Hi
> 
> On Wed, 2 Jan 2013, Philip Avinash wrote:
> 
> > EQEP entry is HWMOD entry is not present in HWMOD entry.
> 
> Patch descriptions need to make sense.  This one does not.  I've fixed it 
> for you this time, but please take more care in the future.
> 
> 
> - Paul
> 
> 
> From: Philip Avinash <avinashphilip@ti.com>
> Date: Wed, 2 Jan 2013 18:54:48 +0530
> Subject: [PATCH] ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD
>  entries
> 
> EQEP IP block integration data is not present in HWMOD data. Also
> address ranges specified for EACP & EHRPWM are not correct & HWMOD
> flags of ADDR_TYPE_RT are added to PWM subsystem register address
> space. This patch:
> 1. Corrects register address mapping for ECAP & EHRPWM
> 2. Removes  HWMOD flags in PWM submodule register address space.
> 3. Adds EQEP HWMOD entries.
> 
> Signed-off-by: Philip Avinash <avinashphilip@ti.com>
> [paul@pwsan.com: tweaked patch description]
> Signed-off-by: Paul Walmsley <paul@pwsan.com>


Feel free to add my Acked-by on this.

Thanks,
Vaibhav

> ---
>  arch/arm/mach-omap2/omap_hwmod_33xx_data.c |  158 +++++++++++++++++++++++++---
>  1 file changed, 145 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index 9e34d4c..4b1cc4d 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -784,7 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
>  };
>  
>  /*
> - * 'epwmss' class: ecap0,1,2,  ehrpwm0,1,2
> + * 'epwmss' class: ehrpwm0,1,2 eqep0,1,2 ecap0,1,2
>   */
>  static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
>  	.rev_offs	= 0x0,
> @@ -864,6 +864,66 @@ static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
>  	},
>  };
>  
> +/* eqep0 */
> +static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
> +	{ .irq = 79 + OMAP_INTC_START, },
> +	{ .irq = -1 },
> +};
> +
> +static struct omap_hwmod am33xx_eqep0_hwmod = {
> +	.name		= "eqep0",
> +	.class		= &am33xx_epwmss_hwmod_class,
> +	.clkdm_name	= "l4ls_clkdm",
> +	.mpu_irqs	= am33xx_eqep0_irqs,
> +	.main_clk	= "l4ls_gclk",
> +	.prcm		= {
> +		.omap4	= {
> +			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
> +			.modulemode	= MODULEMODE_SWCTRL,
> +		},
> +	},
> +};
> +
> +/* eqep1 */
> +static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
> +	{ .irq = 88 + OMAP_INTC_START, },
> +	{ .irq = -1 },
> +};
> +
> +static struct omap_hwmod am33xx_eqep1_hwmod = {
> +	.name		= "eqep1",
> +	.class		= &am33xx_epwmss_hwmod_class,
> +	.clkdm_name	= "l4ls_clkdm",
> +	.mpu_irqs	= am33xx_eqep1_irqs,
> +	.main_clk	= "l4ls_gclk",
> +	.prcm		= {
> +		.omap4	= {
> +			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
> +			.modulemode	= MODULEMODE_SWCTRL,
> +		},
> +	},
> +};
> +
> +/* eqep2 */
> +static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
> +	{ .irq = 89 + OMAP_INTC_START, },
> +	{ .irq = -1 },
> +};
> +
> +static struct omap_hwmod am33xx_eqep2_hwmod = {
> +	.name		= "eqep2",
> +	.class		= &am33xx_epwmss_hwmod_class,
> +	.clkdm_name	= "l4ls_clkdm",
> +	.mpu_irqs	= am33xx_eqep2_irqs,
> +	.main_clk	= "l4ls_gclk",
> +	.prcm		= {
> +		.omap4	= {
> +			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
> +			.modulemode	= MODULEMODE_SWCTRL,
> +		},
> +	},
> +};
> +
>  /* ecap0 */
>  static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
>  	{ .irq = 31 + OMAP_INTC_START, },
> @@ -2559,8 +2619,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48300200,
> -		.pa_end		= 0x48300200 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48300200 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -2585,8 +2644,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48302200,
> -		.pa_end		= 0x48302200 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48302200 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -2611,8 +2669,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48304200,
> -		.pa_end		= 0x48304200 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48304200 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -2629,6 +2686,81 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
>   * Splitting the resources to handle access of PWMSS config space
>   * and module specific part independently
>   */
> +static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
> +	{
> +		.pa_start	= 0x48300000,
> +		.pa_end		= 0x48300000 + SZ_16 - 1,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +	{
> +		.pa_start	= 0x48300180,
> +		.pa_end		= 0x48300180 + SZ_128 - 1,
> +	},
> +	{ }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep0 = {
> +	.master		= &am33xx_l4_ls_hwmod,
> +	.slave		= &am33xx_eqep0_hwmod,
> +	.clk		= "l4ls_gclk",
> +	.addr		= am33xx_eqep0_addr_space,
> +	.user		= OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
> +	{
> +		.pa_start	= 0x48302000,
> +		.pa_end		= 0x48302000 + SZ_16 - 1,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +	{
> +		.pa_start	= 0x48302180,
> +		.pa_end		= 0x48302180 + SZ_128 - 1,
> +	},
> +	{ }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep1 = {
> +	.master		= &am33xx_l4_ls_hwmod,
> +	.slave		= &am33xx_eqep1_hwmod,
> +	.clk		= "l4ls_gclk",
> +	.addr		= am33xx_eqep1_addr_space,
> +	.user		= OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
> +	{
> +		.pa_start	= 0x48304000,
> +		.pa_end		= 0x48304000 + SZ_16 - 1,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +	{
> +		.pa_start	= 0x48304180,
> +		.pa_end		= 0x48304180 + SZ_128 - 1,
> +	},
> +	{ }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep2 = {
> +	.master		= &am33xx_l4_ls_hwmod,
> +	.slave		= &am33xx_eqep2_hwmod,
> +	.clk		= "l4ls_gclk",
> +	.addr		= am33xx_eqep2_addr_space,
> +	.user		= OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
>  static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
>  	{
>  		.pa_start	= 0x48300000,
> @@ -2637,8 +2769,7 @@ static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48300100,
> -		.pa_end		= 0x48300100 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48300100 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -2663,8 +2794,7 @@ static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48302100,
> -		.pa_end		= 0x48302100 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48302100 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -2689,8 +2819,7 @@ static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48304100,
> -		.pa_end		= 0x48304100 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48304100 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -3395,6 +3524,9 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
>  	&am33xx_l4_ls__ehrpwm0,
>  	&am33xx_l4_ls__ehrpwm1,
>  	&am33xx_l4_ls__ehrpwm2,
> +	&am33xx_l4_ls__eqep0,
> +	&am33xx_l4_ls__eqep1,
> +	&am33xx_l4_ls__eqep2,
>  	&am33xx_l4_ls__ecap0,
>  	&am33xx_l4_ls__ecap1,
>  	&am33xx_l4_ls__ecap2,
> -- 
> 1.7.10.4
> 
> 

RE: [PATCH 4/7] ARM: AM33XX: clk: Add clock node for EHRPWM TBCLK

[Philip, Avinash]

On Fri, Feb 08, 2013 at 20:36:53, Paul Walmsley wrote:
> Hi,
> 
> On Wed, 2 Jan 2013, Philip Avinash wrote:
> 
> > EHRPWM module requires explicit clock gating of TBCLK from control
> > module. Hence add TBCLK clock node in clock tree for EHRPWM modules.
> > 
> > Signed-off-by: Philip Avinash <avinashphilip@ti.com>
> 
> This patch adds some sparse[1] warnings:
> 
> > arch/arm/mach-omap2/cclock33xx_data.c:844:1: warning: Using plain 
> integer as NULL pointer
> > arch/arm/mach-omap2/cclock33xx_data.c:850:1: warning: Using plain 
> integer as NULL pointer
> > arch/arm/mach-omap2/cclock33xx_data.c:856:1: warning: Using plain 
> integer as NULL pointer
> 
> Could you fix these, please?

Sorry for late response. I will send an updated version with fix for
sparse warnings.

Thanks
Avinash

> 
> 
> - Paul
> 
> 1. Sparse: https://sparse.wiki.kernel.org/index.php/Main_Page
> 
> 

RE: [PATCH 1/7] ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries

[Philip, Avinash]

On Fri, Feb 08, 2013 at 20:40:18, Paul Walmsley wrote:
> Hi
> 
> On Wed, 2 Jan 2013, Philip Avinash wrote:
> 
> > EQEP entry is HWMOD entry is not present in HWMOD entry.
> 
> Patch descriptions need to make sense.  This one does not.  I've fixed it 
> for you this time, but please take more care in the future.
> 

Thanks for applying this patch & I will take care of the patch description
details.

Thanks
Avinash

> 
> - Paul
> 
> 
> From: Philip Avinash <avinashphilip@ti.com>
> Date: Wed, 2 Jan 2013 18:54:48 +0530
> Subject: [PATCH] ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD
>  entries
> 
> EQEP IP block integration data is not present in HWMOD data. Also
> address ranges specified for EACP & EHRPWM are not correct & HWMOD
> flags of ADDR_TYPE_RT are added to PWM subsystem register address
> space. This patch:
> 1. Corrects register address mapping for ECAP & EHRPWM
> 2. Removes  HWMOD flags in PWM submodule register address space.
> 3. Adds EQEP HWMOD entries.
> 
> Signed-off-by: Philip Avinash <avinashphilip@ti.com>
> [paul@pwsan.com: tweaked patch description]
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_33xx_data.c |  158 +++++++++++++++++++++++++---
>  1 file changed, 145 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index 9e34d4c..4b1cc4d 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -784,7 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
>  };
>  
>  /*
> - * 'epwmss' class: ecap0,1,2,  ehrpwm0,1,2
> + * 'epwmss' class: ehrpwm0,1,2 eqep0,1,2 ecap0,1,2
>   */
>  static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
>  	.rev_offs	= 0x0,
> @@ -864,6 +864,66 @@ static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
>  	},
>  };
>  
> +/* eqep0 */
> +static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
> +	{ .irq = 79 + OMAP_INTC_START, },
> +	{ .irq = -1 },
> +};
> +
> +static struct omap_hwmod am33xx_eqep0_hwmod = {
> +	.name		= "eqep0",
> +	.class		= &am33xx_epwmss_hwmod_class,
> +	.clkdm_name	= "l4ls_clkdm",
> +	.mpu_irqs	= am33xx_eqep0_irqs,
> +	.main_clk	= "l4ls_gclk",
> +	.prcm		= {
> +		.omap4	= {
> +			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
> +			.modulemode	= MODULEMODE_SWCTRL,
> +		},
> +	},
> +};
> +
> +/* eqep1 */
> +static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
> +	{ .irq = 88 + OMAP_INTC_START, },
> +	{ .irq = -1 },
> +};
> +
> +static struct omap_hwmod am33xx_eqep1_hwmod = {
> +	.name		= "eqep1",
> +	.class		= &am33xx_epwmss_hwmod_class,
> +	.clkdm_name	= "l4ls_clkdm",
> +	.mpu_irqs	= am33xx_eqep1_irqs,
> +	.main_clk	= "l4ls_gclk",
> +	.prcm		= {
> +		.omap4	= {
> +			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
> +			.modulemode	= MODULEMODE_SWCTRL,
> +		},
> +	},
> +};
> +
> +/* eqep2 */
> +static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
> +	{ .irq = 89 + OMAP_INTC_START, },
> +	{ .irq = -1 },
> +};
> +
> +static struct omap_hwmod am33xx_eqep2_hwmod = {
> +	.name		= "eqep2",
> +	.class		= &am33xx_epwmss_hwmod_class,
> +	.clkdm_name	= "l4ls_clkdm",
> +	.mpu_irqs	= am33xx_eqep2_irqs,
> +	.main_clk	= "l4ls_gclk",
> +	.prcm		= {
> +		.omap4	= {
> +			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
> +			.modulemode	= MODULEMODE_SWCTRL,
> +		},
> +	},
> +};
> +
>  /* ecap0 */
>  static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
>  	{ .irq = 31 + OMAP_INTC_START, },
> @@ -2559,8 +2619,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48300200,
> -		.pa_end		= 0x48300200 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48300200 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -2585,8 +2644,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48302200,
> -		.pa_end		= 0x48302200 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48302200 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -2611,8 +2669,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48304200,
> -		.pa_end		= 0x48304200 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48304200 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -2629,6 +2686,81 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
>   * Splitting the resources to handle access of PWMSS config space
>   * and module specific part independently
>   */
> +static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
> +	{
> +		.pa_start	= 0x48300000,
> +		.pa_end		= 0x48300000 + SZ_16 - 1,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +	{
> +		.pa_start	= 0x48300180,
> +		.pa_end		= 0x48300180 + SZ_128 - 1,
> +	},
> +	{ }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep0 = {
> +	.master		= &am33xx_l4_ls_hwmod,
> +	.slave		= &am33xx_eqep0_hwmod,
> +	.clk		= "l4ls_gclk",
> +	.addr		= am33xx_eqep0_addr_space,
> +	.user		= OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
> +	{
> +		.pa_start	= 0x48302000,
> +		.pa_end		= 0x48302000 + SZ_16 - 1,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +	{
> +		.pa_start	= 0x48302180,
> +		.pa_end		= 0x48302180 + SZ_128 - 1,
> +	},
> +	{ }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep1 = {
> +	.master		= &am33xx_l4_ls_hwmod,
> +	.slave		= &am33xx_eqep1_hwmod,
> +	.clk		= "l4ls_gclk",
> +	.addr		= am33xx_eqep1_addr_space,
> +	.user		= OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
> +static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
> +	{
> +		.pa_start	= 0x48304000,
> +		.pa_end		= 0x48304000 + SZ_16 - 1,
> +		.flags		= ADDR_TYPE_RT
> +	},
> +	{
> +		.pa_start	= 0x48304180,
> +		.pa_end		= 0x48304180 + SZ_128 - 1,
> +	},
> +	{ }
> +};
> +
> +static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep2 = {
> +	.master		= &am33xx_l4_ls_hwmod,
> +	.slave		= &am33xx_eqep2_hwmod,
> +	.clk		= "l4ls_gclk",
> +	.addr		= am33xx_eqep2_addr_space,
> +	.user		= OCP_USER_MPU,
> +};
> +
> +/*
> + * Splitting the resources to handle access of PWMSS config space
> + * and module specific part independently
> + */
>  static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
>  	{
>  		.pa_start	= 0x48300000,
> @@ -2637,8 +2769,7 @@ static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48300100,
> -		.pa_end		= 0x48300100 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48300100 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -2663,8 +2794,7 @@ static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48302100,
> -		.pa_end		= 0x48302100 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48302100 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -2689,8 +2819,7 @@ static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
>  	},
>  	{
>  		.pa_start	= 0x48304100,
> -		.pa_end		= 0x48304100 + SZ_256 - 1,
> -		.flags		= ADDR_TYPE_RT
> +		.pa_end		= 0x48304100 + SZ_128 - 1,
>  	},
>  	{ }
>  };
> @@ -3395,6 +3524,9 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
>  	&am33xx_l4_ls__ehrpwm0,
>  	&am33xx_l4_ls__ehrpwm1,
>  	&am33xx_l4_ls__ehrpwm2,
> +	&am33xx_l4_ls__eqep0,
> +	&am33xx_l4_ls__eqep1,
> +	&am33xx_l4_ls__eqep2,
>  	&am33xx_l4_ls__ecap0,
>  	&am33xx_l4_ls__ecap1,
>  	&am33xx_l4_ls__ecap2,
> -- 
> 1.7.10.4
> 
>