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From: "Yang, Shunyong" <shunyong.yang@hxt-semitech.com>
To: Sinan Kaya <okaya@kernel.org>
Cc: "andy.gross@linaro.org" <andy.gross@linaro.org>,
	"david.brown@linaro.org" <david.brown@linaro.org>,
	"vkoul@kernel.org" <vkoul@kernel.org>,
	"dan.j.williams@intel.com" <dan.j.williams@intel.com>,
	"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Zheng, Joey" <yu.zheng@hxt-semitech.com>
Subject: Re: [PATCH 2/2] dmaengine: qcom_hidma: assign channel cookie correctly
Date: Fri, 14 Dec 2018 01:03:09 +0000	[thread overview]
Message-ID: <79da1c31d3e14e6e91cf6a7cc0fea31a@HXTBJIDCEMVIW01.hxtcorp.net> (raw)
In-Reply-To: 88ef21bd-4e4f-8cce-39b3-53da45740f0f@kernel.org

Hi, Sinan

On 2018/12/9 4:28, Sinan Kaya wrote:
> On 12/6/2018 11:29 PM, Shunyong Yang wrote:
>> When dma_cookie_complete() is called in hidma_process_completed(),
>> dma_cookie_status() will return DMA_COMPLETE in hidma_tx_status(). Then,
>> hidma_txn_is_success() will be called to use channel cookie
>> mchan->last_success to do additional DMA status check. Current code
>> assigns mchan->last_success after dma_cookie_complete(). This causes
>> a race condition of dma_cookie_status() returns DMA_COMPLETE before
>> mchan->last_success is assigned correctly. The race will cause
>> hidma_tx_status() return DMA_ERROR but the transaction is actually a
>> success. Moreover, in async_tx case, it will cause a timeout panic
>> in async_tx_quiesce().
>>
>>   Kernel panic - not syncing: async_tx_quiesce: DMA error waiting for
>>   transaction
>>   ...
>>   Call trace:
>>   [<ffff000008089994>] dump_backtrace+0x0/0x1f4
>>   [<ffff000008089bac>] show_stack+0x24/0x2c
>>   [<ffff00000891e198>] dump_stack+0x84/0xa8
>>   [<ffff0000080da544>] panic+0x12c/0x29c
>>   [<ffff0000045d0334>] async_tx_quiesce+0xa4/0xc8 [async_tx]
>>   [<ffff0000045d03c8>] async_trigger_callback+0x70/0x1c0 [async_tx]
>>   [<ffff0000048b7d74>] raid_run_ops+0x86c/0x1540 [raid456]
>>   [<ffff0000048bd084>] handle_stripe+0x5e8/0x1c7c [raid456]
>>   [<ffff0000048be9ec>] handle_active_stripes.isra.45+0x2d4/0x550 [raid456]
>>   [<ffff0000048beff4>] raid5d+0x38c/0x5d0 [raid456]
>>   [<ffff000008736538>] md_thread+0x108/0x168
>>   [<ffff0000080fb1cc>] kthread+0x10c/0x138
>>   [<ffff000008084d34>] ret_from_fork+0x10/0x18
>>
>> Cc: Joey Zheng<yu.zheng@hxt-semitech.com>
>> Signed-off-by: Shunyong Yang<shunyong.yang@hxt-semitech.com>
> 
> 
> Acked-by: Sinan Kaya <okaya@kernel.org>
> 
> to both patches 1/2 and 2/2.
> 
> 
Thanks for the ACKs.

Shunyong.


  reply	other threads:[~2018-12-14  1:04 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-07  4:28 [PATCH 1/2] dmaengine: qcom_hidma: initialize tx flags in hidma_prep_dma_* Shunyong Yang
2018-12-07  4:29 ` [PATCH 2/2] dmaengine: qcom_hidma: assign channel cookie correctly Shunyong Yang
2018-12-08 20:28   ` Sinan Kaya
2018-12-14  1:03     ` Yang, Shunyong [this message]
2019-01-04  8:56       ` Yang, Shunyong
2019-01-09  1:35         ` About some mail lost and random unsubscribe issues on this dmaengine list Yang, Shunyong
2019-01-09  6:58           ` Vinod Koul
2019-01-09  7:51             ` Yang, Shunyong
2019-01-09 16:55               ` Theodore Y. Ts'o
2019-01-04 17:31   ` [PATCH 2/2] dmaengine: qcom_hidma: assign channel cookie correctly Vinod Koul

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