From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE423C433EF for ; Mon, 11 Apr 2022 09:07:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344149AbiDKJJ5 (ORCPT ); Mon, 11 Apr 2022 05:09:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344141AbiDKJJx (ORCPT ); Mon, 11 Apr 2022 05:09:53 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 570353EF1F for ; Mon, 11 Apr 2022 02:07:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 3E1291F43465 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1649668058; bh=/BxB8I3hVWgWdEz3fBOpIt5kSfdx7FY5Q3jtn/JageQ=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=iP8/l6eZFGMBCI+fYqrI9frunX10G/bsIaDU5ibF43HYTwGMg/eZrlGuS7KNvP77y M4BrjilcLZd8g+DFp6+yyyCUqRa6SnZN6PtuPBdsGtP6jVkXqV+zeL+w7EnLIj0WaC illhVbc+nbX0wwQqbS/uL20X+VwCyHmQFy/sJJTpx8/8gZCNZ6HT5UxiOWdbLpe5tg Y83tnFtNMIzJHLEPLJJTbtXAVMQt8n6nuNBAAqGXut6PYTr7CHhyCMSAY72Xasjz4g v2dlo1xwHlcYiCbGx/sBByiIr5n341sEMhspVpxMk8nITcHzhWZpVFQ5IWjbgfTnRQ aQ5DyS10zKz4A== Message-ID: <7a4e5afb-6947-ed7f-8555-c7402aaa3a29@collabora.com> Date: Mon, 11 Apr 2022 11:07:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v4, 3/4] drm/mediatek: keep dsi as LP00 before dcs cmds transfer Content-Language: en-US To: xinlei.lee@mediatek.com, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, matthias.bgg@gmail.com, rex-bc.chen@mediatek.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jitao.shi@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com References: <1649644308-8455-1-git-send-email-xinlei.lee@mediatek.com> <1649644308-8455-4-git-send-email-xinlei.lee@mediatek.com> From: AngeloGioacchino Del Regno In-Reply-To: <1649644308-8455-4-git-send-email-xinlei.lee@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Il 11/04/22 04:31, xinlei.lee@mediatek.com ha scritto: > From: Jitao Shi > > To comply with the panel sequence, hold the mipi signal to LP00 before the dcs cmds transmission, > and pull the mipi signal high from LP00 to LP11 until the start of the dcs cmds transmission. > The normal panel timing is : > (1) pp1800 DC pull up > (2) avdd & avee AC pull high > (3) lcm_reset pull high -> pull low -> pull high > (4) Pull MIPI signal high (LP11) -> initial code -> send video data(HS mode) > The power-off sequence is reversed. > If dsi is not in cmd mode, then dsi will pull the mipi signal high in the mtk_output_dsi_enable function. > > Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge API") > > Signed-off-by: Jitao Shi > Signed-off-by: Xinlei Lee > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 28 +++++++++++++++++++++------- > 1 file changed, 21 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index cf76c53a1af6..9ad6f08c8bfe 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -203,6 +203,7 @@ struct mtk_dsi { > struct mtk_phy_timing phy_timing; > int refcount; > bool enabled; > + bool lanes_ready; > u32 irq_data; > wait_queue_head_t irq_wait_queue; > const struct mtk_dsi_driver_data *driver_data; > @@ -654,13 +655,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > - mtk_dsi_clk_ulp_mode_leave(dsi); > - mtk_dsi_lane0_ulp_mode_leave(dsi); > - mtk_dsi_clk_hs_mode(dsi, 0); > - > return 0; > err_disable_engine_clk: > clk_disable_unprepare(dsi->engine_clk); > @@ -689,6 +683,23 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) > clk_disable_unprepare(dsi->digital_clk); > > phy_power_off(dsi->phy); > + > + dsi->lanes_ready = false; > +} > + > +static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) > +{ > + if (!dsi->lanes_ready) { > + dsi->lanes_ready = true; > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > + mtk_dsi_clk_ulp_mode_leave(dsi); > + mtk_dsi_lane0_ulp_mode_leave(dsi); > + mtk_dsi_clk_hs_mode(dsi, 0); > + msleep(20); This is a very long sleep, which wasn't present before this change. Please document the reasons why we need this 20ms sleep with a comment in the code. Regards, Angelo