From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDC63C43219 for ; Mon, 6 Dec 2021 16:02:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1444667AbhLFQFM (ORCPT ); Mon, 6 Dec 2021 11:05:12 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:36202 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1444070AbhLFQCC (ORCPT ); Mon, 6 Dec 2021 11:02:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1638806314; x=1670342314; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=eBsoCOieGRxUqBCU/SfO7UQSeK/mQGz2GwEs7g1Ifbo=; b=KwRB70mSTljF7TwvhlzATMTdlsBTqKTrz1Fw+GMvodTcTErH+CaaO1Ze tAmzlvP86HXHFQPZgihxSg+6cKxYlKXqBDwJyeoVNytY55H3GJUgOaekE wjMtdBQkWgrQaypmLSHiVGJ6/FNzJdzi7APS2O8TPOGuQSw3LoBfHdYCb s=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 06 Dec 2021 07:58:32 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2021 07:58:31 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 6 Dec 2021 07:58:31 -0800 Received: from [10.50.43.186] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 6 Dec 2021 07:58:23 -0800 Message-ID: <7a8c0ef8-ce09-a3d7-90e9-d401f2feaec7@quicinc.com> Date: Mon, 6 Dec 2021 21:27:48 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.1.2 Subject: Re: [PATCHv5 1/4] arm64: io: Use asm-generic high level MMIO accessors Content-Language: en-US To: Arnd Bergmann CC: Will Deacon , Catalin Marinas , Steven Rostedt , Marc Zyngier , gregkh , Linux Kernel Mailing List , Linux ARM , linux-arm-msm , References: <7b2b5888-c2ca-2ca0-8c0c-32128fcb37d2@quicinc.com> <2efe933e-de1e-0dfc-959a-c0003e28f830@quicinc.com> From: Sai Prakash Ranjan In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/6/2021 8:45 PM, Arnd Bergmann wrote: > On Mon, Dec 6, 2021 at 2:52 PM Sai Prakash Ranjan > wrote: >> Sorry, what I meant was the literal name of these macros, i.e., >> __iormb() has more explicit naming as >> IO read memory barrier and __io_ar() is IO after read? So doesn't it >> make more sense that __iormb() >> should be the primary definition which is already the case and ar/bw >> should be based on them. > My reasoning was that we should ideally only have one set, and that > __io_ar()/__io_bw() are the ones used in architecture-independent code, > so I'd rather use those and deprecate the arm64 specific ones, eventually > moving all the arm64 specific code to use those directly where needed. > > Arnd Ah ok, good enough. I will do this in the next version. Thanks, Sai