From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB72EC55179 for ; Thu, 22 Oct 2020 11:11:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A06E22267 for ; Thu, 22 Oct 2020 11:11:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="mGfND+a8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2897062AbgJVLK7 (ORCPT ); Thu, 22 Oct 2020 07:10:59 -0400 Received: from m42-4.mailgun.net ([69.72.42.4]:14406 "EHLO m42-4.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2897053AbgJVLK7 (ORCPT ); Thu, 22 Oct 2020 07:10:59 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1603365058; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=QZRrrIlsSik5kNZtuDQBF6eUWii+LPf4S5n/hpiEEGM=; b=mGfND+a8IlyQXQCLRdb/s7RCr2FXk6KPmcX3PdfTkGMCSQBEcOvTbH8bwchyRjVmTbktEYvl uDkmU8Hk16YtUORapwVhpMbUpi51LgdqHmeiCk7eYgVhjju3i9MRxhz8z50SPaZBd5LAk7J8 kZO/YcI9Df0OCfLysXVvlsa0IHA= X-Mailgun-Sending-Ip: 69.72.42.4 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 5f9168b2e9e942744cbe6672 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 22 Oct 2020 11:10:42 GMT Sender: saiprakash.ranjan=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 739E0C43382; Thu, 22 Oct 2020 11:10:41 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id AA56CC433CB; Thu, 22 Oct 2020 11:10:40 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Thu, 22 Oct 2020 16:40:40 +0530 From: Sai Prakash Ranjan To: Mathieu Poirier , Suzuki K Poulose , Mike Leach , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, Stephen Boyd , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCHv2 0/4] coresight: etf/etb10/etr: Fix NULL pointer dereference crashes In-Reply-To: References: Message-ID: <7c3e8fe0e506a04c305e710e8e83ca66@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2020-10-22 16:27, Sai Prakash Ranjan wrote: > There was a report of NULL pointer dereference in ETF enable > path for perf CS mode with PID monitoring. It is almost 100% > reproducible when the process to monitor is something very > active such as chrome and with ETF as the sink and not ETR. > Currently in a bid to find the pid, the owner is dereferenced > via task_pid_nr() call in tmc_enable_etf_sink_perf() and with > owner being NULL, we get a NULL pointer dereference. > > Looking at the ETR and other places in the kernel, ETF and the > ETB are the only places trying to dereference the task(owner) > in tmc_enable_etf_sink_perf() which is also called from the > sched_in path as in the call trace. Owner(task) is NULL even > in the case of ETR in tmc_enable_etr_sink_perf(), but since we > cache the PID in alloc_buffer() callback and it is done as part > of etm_setup_aux() when allocating buffer for ETR sink, we never > dereference this NULL pointer and we are safe. So lets do the > same thing with ETF and ETB and cache the PID to which the > cs_buffer belongs in alloc_buffer() callback for ETF and ETB as > done for ETR. This will also remove the unnecessary function calls > (task_pid_nr()) in tmc_enable_etr_sink_perf() and etb_enable_perf(). > > In addition to this, add a check to validate event->owner before > dereferencing it in ETR, ETB and ETF to avoid any possible NULL > pointer dereference crashes in their corresponding alloc_buffer > callbacks and check for kernel events as well. > > Easily reproducible running below: > > perf record -e cs_etm/@tmc_etf0/ -N -p > > Unable to handle kernel NULL pointer dereference at virtual address > 0000000000000548 > Mem abort info: > ESR = 0x96000006 > EC = 0x25: DABT (current EL), IL = 32 bits > SET = 0, FnV = 0 > EA = 0, S1PTW = 0 > Data abort info: > ISV = 0, ISS = 0x00000006 > CM = 0, WnR = 0 > ... > Call trace: > tmc_enable_etf_sink+0xe4/0x280 > coresight_enable_path+0x168/0x1fc > etm_event_start+0x8c/0xf8 > etm_event_add+0x38/0x54 > event_sched_in+0x194/0x2ac > group_sched_in+0x54/0x12c > flexible_sched_in+0xd8/0x120 > visit_groups_merge+0x100/0x16c > ctx_flexible_sched_in+0x50/0x74 > ctx_sched_in+0xa4/0xa8 > perf_event_sched_in+0x60/0x6c > perf_event_context_sched_in+0x98/0xe0 > __perf_event_task_sched_in+0x5c/0xd8 > finish_task_switch+0x184/0x1cc > schedule_tail+0x20/0xec > ret_from_fork+0x4/0x18 > > Sai Prakash Ranjan (4): > perf/core: Export is_kernel_event() > coresight: tmc-etf: Fix NULL ptr dereference in > tmc_enable_etf_sink_perf() > coresight: etb10: Fix possible NULL ptr dereference in > etb_enable_perf() > coresight: tmc-etr: Fix possible NULL ptr dereference in > get_perf_etr_buf_cpu_wide() > > drivers/hwtracing/coresight/coresight-etb10.c | 8 +++++++- > drivers/hwtracing/coresight/coresight-priv.h | 2 ++ > drivers/hwtracing/coresight/coresight-tmc-etf.c | 8 +++++++- > drivers/hwtracing/coresight/coresight-tmc-etr.c | 6 +++++- > include/linux/perf_event.h | 2 ++ > kernel/events/core.c | 3 ++- > 6 files changed, 25 insertions(+), 4 deletions(-) > > > base-commit: f4cb5e9daedf56671badc93ac7f364043aa33886 Please ignore this series, I will need to resend. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation