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Linux x86_64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.4.1 From: Adrian Hunter Subject: Re: [PATCH V5 17/26] mmc: sdhci-uhs2: add clock operations To: Victor Shih , ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang References: <20221019110647.11076-1-victor.shih@genesyslogic.com.tw> <20221019110647.11076-18-victor.shih@genesyslogic.com.tw> Content-Language: en-US Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <20221019110647.11076-18-victor.shih@genesyslogic.com.tw> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19/10/22 14:06, Victor Shih wrote: > This is a sdhci version of mmc's uhs2_[enable|disable]_clk operations. > > Signed-off-by: Ben Chuang > Signed-off-by: AKASHI Takahiro > Signed-off-by: Victor Shih > --- > drivers/mmc/host/sdhci-uhs2.c | 36 +++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c > index 9ceae552c323..afaca5d96938 100644 > --- a/drivers/mmc/host/sdhci-uhs2.c > +++ b/drivers/mmc/host/sdhci-uhs2.c > @@ -11,6 +11,7 @@ > */ > > #include > +#include > #include > > #include "sdhci.h" > @@ -403,6 +404,37 @@ int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > return 0; > } > > +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc) > +{ > + struct sdhci_host *host = mmc_priv(mmc); > + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > + > + clk &= ~SDHCI_CLOCK_CARD_EN; > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > + > + return 0; > +} > + > +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc) > +{ > + struct sdhci_host *host = mmc_priv(mmc); > + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > + u32 val; > + /* 20ms */ > + int timeout_us = 20000; > + > + clk |= SDHCI_CLOCK_CARD_EN; > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > + > + if (read_poll_timeout_atomic(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE), > + 10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) { > + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); > + sdhci_dumpregs(host); > + return 1; > + } > + return 0; > +} > + > /*****************************************************************************\ > * * > * Driver init/exit * > @@ -560,6 +592,10 @@ static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) > > if (!host->mmc_host_ops.uhs2_detect_init) > host->mmc_host_ops.uhs2_detect_init = sdhci_uhs2_do_detect_init; > + if (!host->mmc_host_ops.uhs2_disable_clk) > + host->mmc_host_ops.uhs2_disable_clk = sdhci_uhs2_disable_clk; > + if (!host->mmc_host_ops.uhs2_enable_clk) > + host->mmc_host_ops.uhs2_enable_clk = sdhci_uhs2_enable_clk; As mentioned before ->uhs2_disable_clk() and ->uhs2_enable_clk() are never called. > > return 0; > }