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Thu, 13 Feb 2020 00:13:08 -0800 Received: from xsj-pvapsmtp01 (mailhost.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 01D8CwUL009191; Thu, 13 Feb 2020 00:12:58 -0800 Received: from [172.30.17.107] by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1j29cI-0000u9-CS; Thu, 13 Feb 2020 00:12:58 -0800 Subject: Re: [PATCH 0/7] microblaze: Define SMP safe operations To: Peter Zijlstra , Michal Simek Cc: linux-kernel@vger.kernel.org, monstr@monstr.eu, git@xilinx.com, arnd@arndb.de, Allison Randal , Andrew Morton , Boqun Feng , Enrico Weigelt , Greg Kroah-Hartman , Ingo Molnar , Kate Stewart , Masahiro Yamada , Mike Rapoport , Shubhrajyoti Datta , Stefan Asserhall , Thomas Gleixner , Will Deacon References: <20200212160852.GC14973@hirez.programming.kicks-ass.net> <8dc57ea5-0868-0707-25a7-4cd6d8a43add@xilinx.com> <20200213081139.GG14897@hirez.programming.kicks-ass.net> From: Michal Simek Message-ID: <7de2f55d-a5ee-0aae-3b53-ed39d2b7b38a@xilinx.com> Date: Thu, 13 Feb 2020 09:12:54 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200213081139.GG14897@hirez.programming.kicks-ass.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(376002)(39860400002)(136003)(396003)(346002)(189003)(199004)(5660300002)(70206006)(70586007)(8936002)(81166006)(66574012)(9786002)(8676002)(6666004)(356004)(4326008)(81156014)(316002)(36756003)(426003)(966005)(336012)(110136005)(7416002)(54906003)(26005)(478600001)(31696002)(44832011)(2616005)(2906002)(31686004)(186003);DIR:OUT;SFP:1101;SCL:1;SRVR:BY5PR02MB6851;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 939ca538-174b-46ff-120a-08d7b05c927a X-MS-TrafficTypeDiagnostic: BY5PR02MB6851: X-LD-Processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-Forefront-PRVS: 031257FE13 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2auIxPu7R4b9+oO0CaaPI8RQrKUNZnKaIgLQcYucT43Zmn5i1IY/4dSX6DEFr0zqT+zQ3ANOSJDYmM6bhUw15zmWduRhJws3L7QatefiPnsgOozFH5XYpvKRmDR1IFQpfxU+oNoy+uIIEDuVFzJa3OSj47QOuoQY8B1UpQw/fJwnYswAFYRNZlc8mdg0nchxRGUtxgrQ0MuYjv3bJzwbKex8r/TxDHYhssPKemYD9RTAJWN6yq0z5HFB6p9DW9MS9ERkUBzOuPs0BpTID5Mbn53O0JAbQYgi1XXBXFo6eG5BckEq/rftfmomPcz7qLm3ODJrJLJLn07kI8he8hUKd+NfLzPgsixzLObtXRkhqgFBCwMxLlQokMUPS0yaI8VXyFfPIBOsxGaTlVB0NCzn3g7QKvODGMLAkQXUpLBduv26xDGrxyTfRHGtLBrn9+UQS7JA1E1IIDrjdjuCdqBN7dtbmbE/PojwzMw9Bu218L+Oe8TKJnK5vRujLSoNj0Esuk6hmfBuF4LlDQLnjQO9kw== X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 08:13:13.5446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 939ca538-174b-46ff-120a-08d7b05c927a X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6851 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13. 02. 20 9:11, Peter Zijlstra wrote: > On Thu, Feb 13, 2020 at 08:49:40AM +0100, Michal Simek wrote: >> On 12. 02. 20 17:08, Peter Zijlstra wrote: >>> On Wed, Feb 12, 2020 at 04:42:22PM +0100, Michal Simek wrote: >>> >>>> Microblaze has 32bit exclusive load/store instructions which should be used >>>> instead of irq enable/disable. For more information take a look at >>>> https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug984-vivado-microblaze-ref.pdf >>>> starting from page 25. >>> >>>> arch/microblaze/include/asm/Kbuild | 1 - >>>> arch/microblaze/include/asm/atomic.h | 265 ++++++++++++++++++- >>>> arch/microblaze/include/asm/bitops.h | 189 +++++++++++++ >>>> arch/microblaze/include/asm/cmpxchg.h | 87 ++++++ >>>> arch/microblaze/include/asm/cpuinfo.h | 2 +- >>>> arch/microblaze/include/asm/pgtable.h | 19 +- >>>> arch/microblaze/include/asm/spinlock.h | 240 +++++++++++++++++ >>>> arch/microblaze/include/asm/spinlock_types.h | 25 ++ >>>> arch/microblaze/kernel/cpu/cache.c | 154 ++++++----- >>>> arch/microblaze/kernel/cpu/cpuinfo.c | 38 ++- >>>> arch/microblaze/kernel/cpu/mb.c | 207 ++++++++------- >>>> arch/microblaze/kernel/timer.c | 2 +- >>>> arch/microblaze/mm/consistent.c | 8 +- >>>> 13 files changed, 1040 insertions(+), 197 deletions(-) >>>> create mode 100644 arch/microblaze/include/asm/bitops.h >>>> create mode 100644 arch/microblaze/include/asm/spinlock.h >>>> create mode 100644 arch/microblaze/include/asm/spinlock_types.h >>> >>> I'm missing asm/barrier.h >> >> This has been sent in previous patchset. Link was in this email. > > lkml.org link, please don't use them. The kernel.org links (example > below) have the Message-Id in them, which allows me to search for them > in my local storage without having to use a web browser. > > You mean this one, right? > > https://lkml.kernel.org/r/be707feb95d65b44435a0d9de946192f1fef30c6.1581497860.git.michal.simek@xilinx.com > > So the PDF says this is a completion barrier, needed for DMA. This is a > very expensive option for smp_mb(), but if it is all you have and is > required, then yes, that should do. Yes that's the one. Thanks, Michal