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* [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl
@ 2022-01-25 17:11 Adam Ford
  2022-01-25 17:11 ` [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference Adam Ford
                   ` (10 more replies)
  0 siblings, 11 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Adam Ford, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

Both the i.MX8MQ and i.MX8MM have G1 and G2 decoders.
The two decoders are similar, but the imx8mm lacks the
post-processor, so they will have distinct compatible flags.

From what I can tell, the G2 decoder wasn't working, so splitting
the i.MX8MQ VPU into G1 and G2 makes it easier to control them
independently since the TRM of both the i.MX8MQ and
i.MX8MM list them as distinct IP blocks. This also allowed G2 to
become available.

With them being split, the power-domain can shift to the
vpu-blk-ctrl which is available on both i.MX8MQ and i.MX8MM,
but some of bits are different, so they'll have separate bindings.

Lastly, with the G1 and G2 operational, enable the i.MX8MM.
On the i.MX8MM, the clock speed of 600MHz was chosen to match
the default of the kernel repo from NXP and can be overwritten
by board files for anyone who under/over volts the power rail.

There seems to be some disagreement between the TRM and the Datasheet
for the imx8mq as to whether the speed should be 300MHz (TRM) or
600MHz (datasheet), so feedback from NXP would be very much
appreciated.

The repo used as the starting point was:
5.17-rc1

Fluster was run on both i.MX8MM and i.MX8MQ

At 600 MHz, the i.MX8MM had the following:

./fluster.py run -d GStreamer-VP8-V4L2SL-Gst1.0
Ran 55/61 tests successfully               in 8.299 secs

./fluster.py run -dGStreamer-H.264-V4L2SL-Gst1.0
Ran 90/135 tests successfully               in 71.200 secs

./fluster.py run -d GStreamer-VP9-V4L2SL-Gst1.0
Ran 139/303 tests successfully               in 218.079 secs

The i.MX8MQ had the following:

./fluster.py run -d GStreamer-VP8-V4L2SL-Gst1.0
Ran 55/61 tests successfully               in 7.732 secs

./fluster.py run -dGStreamer-H.264-V4L2SL-Gst1.0
Ran 90/135 tests successfully               in 58.558 secs

./fluster.py run -d GStreamer-VP9-V4L2SL-Gst1.0
Ran 144/303 tests successfully               in 271.373 secs

V4:  Add a comment and a notice based on feedback from Ezequiel Garcia
     if the older compatible flag is used.
     Add new patch which removes a reference to vpu from imx8mq-tqma8mq
     because the VPU is enabled by default and it's not needed.  Without
     this change, its device tree would fail to build.

V3:  Rebase on 5.17-RC1.
     Remove imx8mm-vpu-g2 since it's identical to imx8mq-vpu-g2
     Remove unnecessary examples in YAML files.
     Remove some unused variables.

V2:  Remove references to legacy dt-binding from YAML, but keep
     it in the driver so older device trees can still be used.
     Fix typos in YAML
     Remove reg-names, interrupt-names, and clock-names from YAML,
     since each node will only have one of each, they're not necessary
     Add Fluster scores to cover letter for i.MX8MQ



Adam Ford (8):
  arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
  dt-bindings: media: nxp, imx8mq-vpu: Split G1 and G2 nodes
  media: hantro: Allow i.MX8MQ G1 and G2 to run independently
  arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  arm64: dts: imx8mm: Fix VPU Hanging
  dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm
  media: hantro: Add support for i.MX8MM Hantro-G1
  arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders

Lucas Stach (3):
  dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
  dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl
  soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl

 .../bindings/media/nxp,imx8mq-vpu.yaml        | 68 ++++++++----------
 .../soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml      | 71 +++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 23 +++++-
 .../boot/dts/freescale/imx8mq-tqma8mq.dtsi    |  4 --
 arch/arm64/boot/dts/freescale/imx8mq.dtsi     | 63 +++++++++-------
 drivers/soc/imx/imx8m-blk-ctrl.c              | 66 +++++++++++++++++
 drivers/staging/media/hantro/hantro_drv.c     | 11 +++
 drivers/staging/media/hantro/hantro_hw.h      |  2 +
 drivers/staging/media/hantro/imx8m_vpu_hw.c   | 62 ++++++++++++----
 include/dt-bindings/power/imx8mq-power.h      |  3 +
 10 files changed, 292 insertions(+), 81 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml


base-commit: e783362eb54cd99b2cac8b3a9aeac942e6f6ac07
-- 
2.32.0


^ permalink raw reply	[flat|nested] 44+ messages in thread

* [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-01-25 18:22   ` Lucas Stach
                     ` (3 more replies)
  2022-01-25 17:11 ` [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains Adam Ford
                   ` (9 subsequent siblings)
  10 siblings, 4 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Adam Ford, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

The vpu is enabled by default, so there is no need to manually
enable it.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
index 8aedcddfeab8..38ffcd145b33 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
@@ -272,10 +272,6 @@ &usdhc1 {
 	status = "okay";
 };
 
-&vpu {
-	status = "okay";
-};
-
 /* Attention: wdog reset forcing POR needs baseboard support */
 &wdog1 {
 	status = "okay";
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
  2022-01-25 17:11 ` [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-01-27  8:46   ` Hans Verkuil
  2022-02-09  7:14   ` Shawn Guo
  2022-01-25 17:11 ` [PATCH V4 03/11] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl Adam Ford
                   ` (8 subsequent siblings)
  10 siblings, 2 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Lucas Stach, Rob Herring, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

From: Lucas Stach <l.stach@pengutronix.de>

This adds the defines for the power domains provided by the VPU
blk-ctrl on the i.MX8MQ.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>

diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h
index 8a513bd9166e..9f7d0f1e7c32 100644
--- a/include/dt-bindings/power/imx8mq-power.h
+++ b/include/dt-bindings/power/imx8mq-power.h
@@ -18,4 +18,7 @@
 #define IMX8M_POWER_DOMAIN_MIPI_CSI2	9
 #define IMX8M_POWER_DOMAIN_PCIE2	10
 
+#define IMX8MQ_VPUBLK_PD_G1		0
+#define IMX8MQ_VPUBLK_PD_G2		1
+
 #endif
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* [PATCH V4 03/11] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
  2022-01-25 17:11 ` [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference Adam Ford
  2022-01-25 17:11 ` [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-02-09  7:16   ` Shawn Guo
  2022-01-25 17:11 ` [PATCH V4 04/11] soc: imx: imx8m-blk-ctrl: add " Adam Ford
                   ` (7 subsequent siblings)
  10 siblings, 1 reply; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Lucas Stach, Adam Ford, Rob Herring,
	Ezequiel Garcia, Philipp Zabel, Mauro Carvalho Chehab,
	Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
	Fabio Estevam, NXP Linux Team, Greg Kroah-Hartman,
	linux-rockchip, devicetree, linux-arm-kernel, linux-kernel,
	linux-staging

From: Lucas Stach <l.stach@pengutronix.de>

This adds the DT binding for the i.MX8MQ VPU blk-ctrl.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml
new file mode 100644
index 000000000000..7263ebedf09f
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MQ VPU blk-ctrl
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+  The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to
+  the NoC and ensuring proper power sequencing of the VPU peripherals
+  located in the VPU domain of the SoC.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8mq-vpu-blk-ctrl
+
+  reg:
+    maxItems: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  power-domains:
+    minItems: 3
+    maxItems: 3
+
+  power-domain-names:
+    items:
+      - const: bus
+      - const: g1
+      - const: g2
+
+  clocks:
+    minItems: 2
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: g1
+      - const: g2
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/power/imx8mq-power.h>
+
+    vpu_blk_ctrl: blk-ctrl@38320000 {
+      compatible = "fsl,imx8mq-vpu-blk-ctrl";
+      reg = <0x38320000 0x100>;
+      power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
+      power-domain-names = "bus", "g1", "g2";
+      clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+               <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+      clock-names = "g1", "g2";
+      #power-domain-cells = <1>;
+    };
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* [PATCH V4 04/11] soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
                   ` (2 preceding siblings ...)
  2022-01-25 17:11 ` [PATCH V4 03/11] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-02-09  7:19   ` Shawn Guo
  2022-01-25 17:11 ` [PATCH V4 05/11] dt-bindings: media: nxp, imx8mq-vpu: Split G1 and G2 nodes Adam Ford
                   ` (6 subsequent siblings)
  10 siblings, 1 reply; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Lucas Stach, Adam Ford, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

From: Lucas Stach <l.stach@pengutronix.de>

This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to
avoid putting more of this functionality into the decoder driver.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 511e74f0db8a..122f9c884b38 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -15,6 +15,7 @@
 
 #include <dt-bindings/power/imx8mm-power.h>
 #include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/power/imx8mq-power.h>
 
 #define BLK_SFT_RSTN	0x0
 #define BLK_CLK_EN	0x4
@@ -589,6 +590,68 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
 };
 
+static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
+				     unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/*
+	 * The ADB in the VPUMIX domain has no separate reset and clock
+	 * enable bits, but is ungated and reset together with the VPUs. The
+	 * reset and clock enable inputs to the ADB is a logical OR of the
+	 * VPU bits. In order to set the G2 fuse bits, the G2 clock must
+	 * also be enabled.
+	 */
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1));
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1));
+
+	if (action == GENPD_NOTIFY_ON) {
+		/*
+		 * On power up we have no software backchannel to the GPC to
+		 * wait for the ADB handshake to happen, so we just delay for a
+		 * bit. On power down the GPC driver waits for the handshake.
+		 */
+		udelay(5);
+
+		/* set "fuse" bits to enable the VPUs */
+		regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
+		regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
+	}
+
+	return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = {
+	[IMX8MQ_VPUBLK_PD_G1] = {
+		.name = "vpublk-g1",
+		.clk_names = (const char *[]){ "g1", },
+		.num_clks = 1,
+		.gpc_name = "g1",
+		.rst_mask = BIT(1),
+		.clk_mask = BIT(1),
+	},
+	[IMX8MQ_VPUBLK_PD_G2] = {
+		.name = "vpublk-g2",
+		.clk_names = (const char *[]){ "g2", },
+		.num_clks = 1,
+		.gpc_name = "g2",
+		.rst_mask = BIT(0),
+		.clk_mask = BIT(0),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = {
+	.max_reg = 0x14,
+	.power_notifier_fn = imx8mq_vpu_power_notifier,
+	.domains = imx8mq_vpu_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data),
+};
+
 static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	{
 		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
@@ -599,6 +662,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	}, {
 		.compatible = "fsl,imx8mn-disp-blk-ctrl",
 		.data = &imx8mn_disp_blk_ctl_dev_data
+	}, {
+		.compatible = "fsl,imx8mq-vpu-blk-ctrl",
+		.data = &imx8mq_vpu_blk_ctl_dev_data
 	}, {
 		/* Sentinel */
 	}
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* [PATCH V4 05/11] dt-bindings: media: nxp, imx8mq-vpu: Split G1 and G2 nodes
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
                   ` (3 preceding siblings ...)
  2022-01-25 17:11 ` [PATCH V4 04/11] soc: imx: imx8m-blk-ctrl: add " Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-01-25 17:11 ` [PATCH V4 06/11] media: hantro: Allow i.MX8MQ G1 and G2 to run independently Adam Ford
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Adam Ford, Rob Herring, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, Lucas Stach, linux-rockchip,
	devicetree, linux-arm-kernel, linux-kernel, linux-staging

The G1 and G2 are independent and separate decoder blocks
that are enabled by the vpu-blk-ctrl power-domain controller,
which now has a proper driver.

Because these blocks only share the power-domain, and can be
independently fused out, update the bindings to support separate
nodes for the G1 and G2 decoders with vpu-blk-ctrl power-domain
support.

The new DT + old kernel isn't a supported configuration.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
index 762be3f96ce9..9c28d562112b 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
@@ -15,33 +15,20 @@ description:
 
 properties:
   compatible:
-    const: nxp,imx8mq-vpu
+    oneOf:
+      - const: nxp,imx8mq-vpu
+        deprecated: true
+      - const: nxp,imx8mq-vpu-g1
+      - const: nxp,imx8mq-vpu-g2
 
   reg:
-    maxItems: 3
-
-  reg-names:
-    items:
-      - const: g1
-      - const: g2
-      - const: ctrl
+    maxItems: 1
 
   interrupts:
-    maxItems: 2
-
-  interrupt-names:
-    items:
-      - const: g1
-      - const: g2
+    maxItems: 1
 
   clocks:
-    maxItems: 3
-
-  clock-names:
-    items:
-      - const: g1
-      - const: g2
-      - const: bus
+    maxItems: 1
 
   power-domains:
     maxItems: 1
@@ -49,31 +36,33 @@ properties:
 required:
   - compatible
   - reg
-  - reg-names
   - interrupts
-  - interrupt-names
   - clocks
-  - clock-names
 
 additionalProperties: false
 
 examples:
   - |
         #include <dt-bindings/clock/imx8mq-clock.h>
+        #include <dt-bindings/power/imx8mq-power.h>
+        #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+        vpu_g1: video-codec@38300000 {
+                compatible = "nxp,imx8mq-vpu-g1";
+                reg = <0x38300000 0x10000>;
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
+                power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
+        };
+  - |
+        #include <dt-bindings/clock/imx8mq-clock.h>
+        #include <dt-bindings/power/imx8mq-power.h>
         #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-        vpu: video-codec@38300000 {
-                compatible = "nxp,imx8mq-vpu";
-                reg = <0x38300000 0x10000>,
-                      <0x38310000 0x10000>,
-                      <0x38320000 0x10000>;
-                reg-names = "g1", "g2", "ctrl";
-                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "g1", "g2";
-                clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
-                         <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
-                         <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
-                clock-names = "g1", "g2", "bus";
-                power-domains = <&pgc_vpu>;
+        vpu_g2: video-codec@38300000 {
+                compatible = "nxp,imx8mq-vpu-g2";
+                reg = <0x38310000 0x10000>;
+                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+                power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
         };
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* [PATCH V4 06/11] media: hantro: Allow i.MX8MQ G1 and G2 to run independently
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
                   ` (4 preceding siblings ...)
  2022-01-25 17:11 ` [PATCH V4 05/11] dt-bindings: media: nxp, imx8mq-vpu: Split G1 and G2 nodes Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-01-25 17:11 ` [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Adam Ford
                   ` (4 subsequent siblings)
  10 siblings, 0 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Adam Ford, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

The VPU in the i.MX8MQ is really the combination of Hantro G1 and
Hantro G2. With the updated vpu-blk-ctrl, the power domains system
can enable and disable them separately as well as pull them out of
reset. This simplifies the code and lets them run independently
while still retaining backwards compatibility with older device
trees for those using G1.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
index 6a51f39dde56..f56e8b3efada 100644
--- a/drivers/staging/media/hantro/hantro_drv.c
+++ b/drivers/staging/media/hantro/hantro_drv.c
@@ -616,6 +616,7 @@ static const struct of_device_id of_hantro_match[] = {
 #endif
 #ifdef CONFIG_VIDEO_HANTRO_IMX8M
 	{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
+	{ .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant },
 	{ .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
 #endif
 #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4
@@ -890,6 +891,15 @@ static int hantro_probe(struct platform_device *pdev)
 	match = of_match_node(of_hantro_match, pdev->dev.of_node);
 	vpu->variant = match->data;
 
+	/*
+	 * Support for nxp,imx8mq-vpu is kept for backwards compatibility
+	 * but it's deprecated. Please update your DTS file to use
+	 * nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead.
+	 */
+	if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu"))
+		dev_warn(&pdev->dev, "%s compatible is deprecated\n",
+			 match->compatible);
+
 	INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog);
 
 	vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks,
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
index 4a19ae8940b9..f0bd2ffe290b 100644
--- a/drivers/staging/media/hantro/hantro_hw.h
+++ b/drivers/staging/media/hantro/hantro_hw.h
@@ -299,6 +299,7 @@ enum hantro_enc_fmt {
 	ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3,
 };
 
+extern const struct hantro_variant imx8mq_vpu_g1_variant;
 extern const struct hantro_variant imx8mq_vpu_g2_variant;
 extern const struct hantro_variant imx8mq_vpu_variant;
 extern const struct hantro_variant px30_vpu_variant;
diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
index f5991b8e553a..849ea7122d47 100644
--- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
@@ -205,13 +205,6 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx)
 	imx8m_soft_reset(vpu, RESET_G1);
 }
 
-static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx)
-{
-	struct hantro_dev *vpu = ctx->dev;
-
-	imx8m_soft_reset(vpu, RESET_G2);
-}
-
 /*
  * Supported codec ops.
  */
@@ -237,17 +230,33 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = {
 	},
 };
 
+static const struct hantro_codec_ops imx8mq_vpu_g1_codec_ops[] = {
+	[HANTRO_MODE_MPEG2_DEC] = {
+		.run = hantro_g1_mpeg2_dec_run,
+		.init = hantro_mpeg2_dec_init,
+		.exit = hantro_mpeg2_dec_exit,
+	},
+	[HANTRO_MODE_VP8_DEC] = {
+		.run = hantro_g1_vp8_dec_run,
+		.init = hantro_vp8_dec_init,
+		.exit = hantro_vp8_dec_exit,
+	},
+	[HANTRO_MODE_H264_DEC] = {
+		.run = hantro_g1_h264_dec_run,
+		.init = hantro_h264_dec_init,
+		.exit = hantro_h264_dec_exit,
+	},
+};
+
 static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = {
 	[HANTRO_MODE_HEVC_DEC] = {
 		.run = hantro_g2_hevc_dec_run,
-		.reset = imx8m_vpu_g2_reset,
 		.init = hantro_hevc_dec_init,
 		.exit = hantro_hevc_dec_exit,
 	},
 	[HANTRO_MODE_VP9_DEC] = {
 		.run = hantro_g2_vp9_dec_run,
 		.done = hantro_g2_vp9_dec_done,
-		.reset = imx8m_vpu_g2_reset,
 		.init = hantro_vp9_dec_init,
 		.exit = hantro_vp9_dec_exit,
 	},
@@ -267,6 +276,8 @@ static const struct hantro_irq imx8mq_g2_irqs[] = {
 
 static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" };
 static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" };
+static const char * const imx8mq_g1_clk_names[] = { "g1" };
+static const char * const imx8mq_g2_clk_names[] = { "g2" };
 
 const struct hantro_variant imx8mq_vpu_variant = {
 	.dec_fmts = imx8m_vpu_dec_fmts,
@@ -287,6 +298,21 @@ const struct hantro_variant imx8mq_vpu_variant = {
 	.num_regs = ARRAY_SIZE(imx8mq_reg_names)
 };
 
+const struct hantro_variant imx8mq_vpu_g1_variant = {
+	.dec_fmts = imx8m_vpu_dec_fmts,
+	.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
+	.postproc_fmts = imx8m_vpu_postproc_fmts,
+	.num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts),
+	.postproc_ops = &hantro_g1_postproc_ops,
+	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
+		 HANTRO_H264_DECODER,
+	.codec_ops = imx8mq_vpu_g1_codec_ops,
+	.irqs = imx8mq_irqs,
+	.num_irqs = ARRAY_SIZE(imx8mq_irqs),
+	.clk_names = imx8mq_g1_clk_names,
+	.num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names),
+};
+
 const struct hantro_variant imx8mq_vpu_g2_variant = {
 	.dec_offset = 0x0,
 	.dec_fmts = imx8m_vpu_g2_dec_fmts,
@@ -296,10 +322,8 @@ const struct hantro_variant imx8mq_vpu_g2_variant = {
 	.postproc_ops = &hantro_g2_postproc_ops,
 	.codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER,
 	.codec_ops = imx8mq_vpu_g2_codec_ops,
-	.init = imx8mq_vpu_hw_init,
-	.runtime_resume = imx8mq_runtime_resume,
 	.irqs = imx8mq_g2_irqs,
 	.num_irqs = ARRAY_SIZE(imx8mq_g2_irqs),
-	.clk_names = imx8mq_clk_names,
-	.num_clocks = ARRAY_SIZE(imx8mq_clk_names),
+	.clk_names = imx8mq_g2_clk_names,
+	.num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names),
 };
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
                   ` (5 preceding siblings ...)
  2022-01-25 17:11 ` [PATCH V4 06/11] media: hantro: Allow i.MX8MQ G1 and G2 to run independently Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-01-25 18:20   ` Lucas Stach
                     ` (2 more replies)
  2022-01-25 17:11 ` [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging Adam Ford
                   ` (3 subsequent siblings)
  10 siblings, 3 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Adam Ford, kernel test robot, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, Lucas Stach, linux-rockchip,
	devicetree, linux-arm-kernel, linux-kernel, linux-staging

With the Hantro G1 and G2 now setup to run independently, update
the device tree to allow both to operate.  This requires the
vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
certain clock enabled to handle the gating of the G1 and G2
fuses, the clock-parents and clock-rates for the various VPU's
to be moved into the pgc_vpu because they cannot get re-parented
once enabled, and the pgc_vpu is the highest in the chain.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 2df2510d0118..549b2440f55d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
 					pgc_vpu: power-domain@6 {
 						#power-domain-cells = <0>;
 						reg = <IMX8M_POWER_DOMAIN_VPU>;
-						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
+							 <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+							 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+						assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+								  <&clk IMX8MQ_CLK_VPU_G2>,
+								  <&clk IMX8MQ_CLK_VPU_BUS>,
+								  <&clk IMX8MQ_VPU_PLL_BYPASS>;
+						assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+									 <&clk IMX8MQ_VPU_PLL_OUT>,
+									 <&clk IMX8MQ_SYS1_PLL_800M>,
+									 <&clk IMX8MQ_VPU_PLL>;
+						assigned-clock-rates = <600000000>,
+								       <600000000>,
+								       <800000000>,
+								       <0>;
 					};
 
 					pgc_disp: power-domain@7 {
@@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
 			status = "disabled";
 		};
 
-		vpu: video-codec@38300000 {
-			compatible = "nxp,imx8mq-vpu";
-			reg = <0x38300000 0x10000>,
-			      <0x38310000 0x10000>,
-			      <0x38320000 0x10000>;
-			reg-names = "g1", "g2", "ctrl";
-			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "g1", "g2";
+		vpu_g1: video-codec@38300000 {
+			compatible = "nxp,imx8mq-vpu-g1";
+			reg = <0x38300000 0x10000>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
+			power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
+		};
+
+		vpu_g2: video-codec@38310000 {
+			compatible = "nxp,imx8mq-vpu-g2";
+			reg = <0x38310000 0x10000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+			power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
+		};
+
+		vpu_blk_ctrl: blk-ctrl@38320000 {
+			compatible = "fsl,imx8mq-vpu-blk-ctrl";
+			reg = <0x38320000 0x100>;
+			power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
+			power-domain-names = "bus", "g1", "g2";
 			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
-				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
-				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
-			clock-names = "g1", "g2", "bus";
-			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
-					  <&clk IMX8MQ_CLK_VPU_G2>,
-					  <&clk IMX8MQ_CLK_VPU_BUS>,
-					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
-			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
-						 <&clk IMX8MQ_VPU_PLL_OUT>,
-						 <&clk IMX8MQ_SYS1_PLL_800M>,
-						 <&clk IMX8MQ_VPU_PLL>;
-			assigned-clock-rates = <600000000>, <600000000>,
-					       <800000000>, <0>;
-			power-domains = <&pgc_vpu>;
+				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+			clock-names = "g1", "g2";
+			#power-domain-cells = <1>;
 		};
 
 		pcie0: pcie@33800000 {
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
                   ` (6 preceding siblings ...)
  2022-01-25 17:11 ` [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-01-25 18:19   ` Lucas Stach
  2022-02-09  7:33   ` Shawn Guo
  2022-01-25 17:11 ` [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm Adam Ford
                   ` (2 subsequent siblings)
  10 siblings, 2 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Adam Ford, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

The vpumix power domain has a reset assigned to it, however
when used, it causes a system hang.  Testing has shown that
it does not appear to be needed anywhere.

Fixes: d39d4bb15310 ("arm64: dts: imx8mm: add GPC node")
Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index f77f90ed416f..0c7a72c51a31 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -707,7 +707,6 @@ pgc_vpumix: power-domain@6 {
 						clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
 						assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
 						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
-						resets = <&src IMX8MQ_RESET_VPU_RESET>;
 					};
 
 					pgc_vpu_g1: power-domain@7 {
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
                   ` (7 preceding siblings ...)
  2022-01-25 17:11 ` [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-01-26  6:45   ` (EXT) " Alexander Stein
  2022-02-04 23:16   ` Rob Herring
  2022-01-25 17:11 ` [PATCH V4 10/11] media: hantro: Add support for i.MX8MM Hantro-G1 Adam Ford
  2022-01-25 17:11 ` [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders Adam Ford
  10 siblings, 2 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Adam Ford, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

The i.MX8M mini appears to have a similar G1 decoder but the
post-processing isn't present, so different compatible flag is required.
Since all the other parameters are the same with imx8mq, just add
the new compatible flag to nxp,imx8mq-vpu.yaml.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
index 9c28d562112b..7dc13a4b1805 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
@@ -5,7 +5,7 @@
 $id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#"
 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 
-title: Hantro G1/G2 VPU codecs implemented on i.MX8MQ SoCs
+title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs
 
 maintainers:
   - Philipp Zabel <p.zabel@pengutronix.de>
@@ -20,6 +20,7 @@ properties:
         deprecated: true
       - const: nxp,imx8mq-vpu-g1
       - const: nxp,imx8mq-vpu-g2
+      - const: nxp,imx8mm-vpu-g1
 
   reg:
     maxItems: 1
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* [PATCH V4 10/11] media: hantro: Add support for i.MX8MM Hantro-G1
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
                   ` (8 preceding siblings ...)
  2022-01-25 17:11 ` [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-01-25 17:11 ` [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders Adam Ford
  10 siblings, 0 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Adam Ford, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

The i.MX8MM has a Hantro G1 video decoder similar to the
imx8mq but lacks the post-processor present in the imx8mq.
Add support in the driver for it with the post-processing
removed.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
index f56e8b3efada..8f020ba15194 100644
--- a/drivers/staging/media/hantro/hantro_drv.c
+++ b/drivers/staging/media/hantro/hantro_drv.c
@@ -615,6 +615,7 @@ static const struct of_device_id of_hantro_match[] = {
 	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
 #endif
 #ifdef CONFIG_VIDEO_HANTRO_IMX8M
+	{ .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, },
 	{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
 	{ .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant },
 	{ .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
index f0bd2ffe290b..c00b46e06055 100644
--- a/drivers/staging/media/hantro/hantro_hw.h
+++ b/drivers/staging/media/hantro/hantro_hw.h
@@ -299,6 +299,7 @@ enum hantro_enc_fmt {
 	ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3,
 };
 
+extern const struct hantro_variant imx8mm_vpu_g1_variant;
 extern const struct hantro_variant imx8mq_vpu_g1_variant;
 extern const struct hantro_variant imx8mq_vpu_g2_variant;
 extern const struct hantro_variant imx8mq_vpu_variant;
diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
index 849ea7122d47..9802508bade2 100644
--- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
@@ -327,3 +327,15 @@ const struct hantro_variant imx8mq_vpu_g2_variant = {
 	.clk_names = imx8mq_g2_clk_names,
 	.num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names),
 };
+
+const struct hantro_variant imx8mm_vpu_g1_variant = {
+	.dec_fmts = imx8m_vpu_dec_fmts,
+	.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
+	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
+		 HANTRO_H264_DECODER,
+	.codec_ops = imx8mq_vpu_g1_codec_ops,
+	.irqs = imx8mq_irqs,
+	.num_irqs = ARRAY_SIZE(imx8mq_irqs),
+	.clk_names = imx8mq_g1_clk_names,
+	.num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names),
+};
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders
  2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
                   ` (9 preceding siblings ...)
  2022-01-25 17:11 ` [PATCH V4 10/11] media: hantro: Add support for i.MX8MM Hantro-G1 Adam Ford
@ 2022-01-25 17:11 ` Adam Ford
  2022-01-25 18:21   ` Lucas Stach
  2022-02-09  7:35   ` Shawn Guo
  10 siblings, 2 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 17:11 UTC (permalink / raw)
  To: linux-media
  Cc: aford, cphealy, Adam Ford, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

There are two decoders on the i.MX8M Mini controlled by the
vpu-blk-ctrl.  The G1 supports H264 and VP8 while the
G2 support HEVC and VP9.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 0c7a72c51a31..98aec4421713 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1272,6 +1272,22 @@ gpu_2d: gpu@38008000 {
 			power-domains = <&pgc_gpu>;
 		};
 
+		vpu_g1: video-codec@38300000 {
+			compatible = "nxp,imx8mm-vpu-g1";
+			reg = <0x38300000 0x10000>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
+			power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
+		};
+
+		vpu_g2: video-codec@38310000 {
+			compatible = "nxp,imx8mq-vpu-g2";
+			reg = <0x38310000 0x10000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
+			power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
+		};
+
 		vpu_blk_ctrl: blk-ctrl@38330000 {
 			compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
 			reg = <0x38330000 0x100>;
@@ -1282,6 +1298,12 @@ vpu_blk_ctrl: blk-ctrl@38330000 {
 				 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
 				 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
 			clock-names = "g1", "g2", "h1";
+			assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
+					  <&clk IMX8MM_CLK_VPU_G2>;
+			assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
+						 <&clk IMX8MM_VPU_PLL_OUT>;
+			assigned-clock-rates = <600000000>,
+					       <600000000>;
 			#power-domain-cells = <1>;
 		};
 
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging
  2022-01-25 17:11 ` [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging Adam Ford
@ 2022-01-25 18:19   ` Lucas Stach
  2022-02-09  7:33   ` Shawn Guo
  1 sibling, 0 replies; 44+ messages in thread
From: Lucas Stach @ 2022-01-25 18:19 UTC (permalink / raw)
  To: Adam Ford, linux-media
  Cc: aford, cphealy, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, linux-rockchip, devicetree, linux-arm-kernel,
	linux-kernel, linux-staging

Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> The vpumix power domain has a reset assigned to it, however
> when used, it causes a system hang.  Testing has shown that
> it does not appear to be needed anywhere.
> 
> Fixes: d39d4bb15310 ("arm64: dts: imx8mm: add GPC node")
> Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index f77f90ed416f..0c7a72c51a31 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -707,7 +707,6 @@ pgc_vpumix: power-domain@6 {
>  						clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
>  						assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
>  						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
> -						resets = <&src IMX8MQ_RESET_VPU_RESET>;
>  					};
>  
>  					pgc_vpu_g1: power-domain@7 {



^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-01-25 17:11 ` [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Adam Ford
@ 2022-01-25 18:20   ` Lucas Stach
  2022-01-25 19:04   ` Ezequiel Garcia
  2022-04-25 15:22   ` Martin Kepplinger
  2 siblings, 0 replies; 44+ messages in thread
From: Lucas Stach @ 2022-01-25 18:20 UTC (permalink / raw)
  To: Adam Ford, linux-media
  Cc: aford, cphealy, kernel test robot, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> With the Hantro G1 and G2 now setup to run independently, update
> the device tree to allow both to operate.  This requires the
> vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> certain clock enabled to handle the gating of the G1 and G2
> fuses, the clock-parents and clock-rates for the various VPU's
> to be moved into the pgc_vpu because they cannot get re-parented
> once enabled, and the pgc_vpu is the highest in the chain.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reported-by: kernel test robot <lkp@intel.com>
> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 2df2510d0118..549b2440f55d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
>  					pgc_vpu: power-domain@6 {
>  						#power-domain-cells = <0>;
>  						reg = <IMX8M_POWER_DOMAIN_VPU>;
> -						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> +						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
> +							 <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> +							 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> +						assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> +								  <&clk IMX8MQ_CLK_VPU_G2>,
> +								  <&clk IMX8MQ_CLK_VPU_BUS>,
> +								  <&clk IMX8MQ_VPU_PLL_BYPASS>;
> +						assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> +									 <&clk IMX8MQ_VPU_PLL_OUT>,
> +									 <&clk IMX8MQ_SYS1_PLL_800M>,
> +									 <&clk IMX8MQ_VPU_PLL>;
> +						assigned-clock-rates = <600000000>,
> +								       <600000000>,
> +								       <800000000>,
> +								       <0>;
>  					};
>  
>  					pgc_disp: power-domain@7 {
> @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
>  			status = "disabled";
>  		};
>  
> -		vpu: video-codec@38300000 {
> -			compatible = "nxp,imx8mq-vpu";
> -			reg = <0x38300000 0x10000>,
> -			      <0x38310000 0x10000>,
> -			      <0x38320000 0x10000>;
> -			reg-names = "g1", "g2", "ctrl";
> -			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "g1", "g2";
> +		vpu_g1: video-codec@38300000 {
> +			compatible = "nxp,imx8mq-vpu-g1";
> +			reg = <0x38300000 0x10000>;
> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> +			power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> +		};
> +
> +		vpu_g2: video-codec@38310000 {
> +			compatible = "nxp,imx8mq-vpu-g2";
> +			reg = <0x38310000 0x10000>;
> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> +			power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> +		};
> +
> +		vpu_blk_ctrl: blk-ctrl@38320000 {
> +			compatible = "fsl,imx8mq-vpu-blk-ctrl";
> +			reg = <0x38320000 0x100>;
> +			power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
> +			power-domain-names = "bus", "g1", "g2";
>  			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> -				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> -				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> -			clock-names = "g1", "g2", "bus";
> -			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> -					  <&clk IMX8MQ_CLK_VPU_G2>,
> -					  <&clk IMX8MQ_CLK_VPU_BUS>,
> -					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
> -			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> -						 <&clk IMX8MQ_VPU_PLL_OUT>,
> -						 <&clk IMX8MQ_SYS1_PLL_800M>,
> -						 <&clk IMX8MQ_VPU_PLL>;
> -			assigned-clock-rates = <600000000>, <600000000>,
> -					       <800000000>, <0>;
> -			power-domains = <&pgc_vpu>;
> +				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> +			clock-names = "g1", "g2";
> +			#power-domain-cells = <1>;
>  		};
>  
>  		pcie0: pcie@33800000 {



^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders
  2022-01-25 17:11 ` [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders Adam Ford
@ 2022-01-25 18:21   ` Lucas Stach
  2022-02-09  7:35   ` Shawn Guo
  1 sibling, 0 replies; 44+ messages in thread
From: Lucas Stach @ 2022-01-25 18:21 UTC (permalink / raw)
  To: Adam Ford, linux-media
  Cc: aford, cphealy, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, linux-rockchip, devicetree, linux-arm-kernel,
	linux-kernel, linux-staging

Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> There are two decoders on the i.MX8M Mini controlled by the
> vpu-blk-ctrl.  The G1 supports H264 and VP8 while the
> G2 support HEVC and VP9.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 0c7a72c51a31..98aec4421713 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1272,6 +1272,22 @@ gpu_2d: gpu@38008000 {
>  			power-domains = <&pgc_gpu>;
>  		};
>  
> +		vpu_g1: video-codec@38300000 {
> +			compatible = "nxp,imx8mm-vpu-g1";
> +			reg = <0x38300000 0x10000>;
> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
> +			power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
> +		};
> +
> +		vpu_g2: video-codec@38310000 {
> +			compatible = "nxp,imx8mq-vpu-g2";
> +			reg = <0x38310000 0x10000>;
> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
> +			power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
> +		};
> +
>  		vpu_blk_ctrl: blk-ctrl@38330000 {
>  			compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
>  			reg = <0x38330000 0x100>;
> @@ -1282,6 +1298,12 @@ vpu_blk_ctrl: blk-ctrl@38330000 {
>  				 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
>  				 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
>  			clock-names = "g1", "g2", "h1";
> +			assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
> +					  <&clk IMX8MM_CLK_VPU_G2>;
> +			assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
> +						 <&clk IMX8MM_VPU_PLL_OUT>;
> +			assigned-clock-rates = <600000000>,
> +					       <600000000>;
>  			#power-domain-cells = <1>;
>  		};
>  



^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
  2022-01-25 17:11 ` [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference Adam Ford
@ 2022-01-25 18:22   ` Lucas Stach
  2022-01-25 18:57   ` Ezequiel Garcia
                     ` (2 subsequent siblings)
  3 siblings, 0 replies; 44+ messages in thread
From: Lucas Stach @ 2022-01-25 18:22 UTC (permalink / raw)
  To: Adam Ford, linux-media
  Cc: aford, cphealy, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, linux-rockchip, devicetree, linux-arm-kernel,
	linux-kernel, linux-staging

Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> The vpu is enabled by default, so there is no need to manually
> enable it.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> index 8aedcddfeab8..38ffcd145b33 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> @@ -272,10 +272,6 @@ &usdhc1 {
>  	status = "okay";
>  };
>  
> -&vpu {
> -	status = "okay";
> -};
> -
>  /* Attention: wdog reset forcing POR needs baseboard support */
>  &wdog1 {
>  	status = "okay";



^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
  2022-01-25 17:11 ` [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference Adam Ford
  2022-01-25 18:22   ` Lucas Stach
@ 2022-01-25 18:57   ` Ezequiel Garcia
  2022-01-26  6:42   ` (EXT) " Alexander Stein
  2022-02-09  7:10   ` Shawn Guo
  3 siblings, 0 replies; 44+ messages in thread
From: Ezequiel Garcia @ 2022-01-25 18:57 UTC (permalink / raw)
  To: Adam Ford
  Cc: linux-media, aford, cphealy, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

On Tue, Jan 25, 2022 at 11:11:18AM -0600, Adam Ford wrote:
> The vpu is enabled by default, so there is no need to manually
> enable it.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> 

Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> index 8aedcddfeab8..38ffcd145b33 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> @@ -272,10 +272,6 @@ &usdhc1 {
>  	status = "okay";
>  };
>  
> -&vpu {
> -	status = "okay";
> -};
> -
>  /* Attention: wdog reset forcing POR needs baseboard support */
>  &wdog1 {
>  	status = "okay";
> -- 
> 2.32.0
> 

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-01-25 17:11 ` [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Adam Ford
  2022-01-25 18:20   ` Lucas Stach
@ 2022-01-25 19:04   ` Ezequiel Garcia
  2022-01-25 19:08     ` Adam Ford
  2022-02-09  7:27     ` Shawn Guo
  2022-04-25 15:22   ` Martin Kepplinger
  2 siblings, 2 replies; 44+ messages in thread
From: Ezequiel Garcia @ 2022-01-25 19:04 UTC (permalink / raw)
  To: Adam Ford
  Cc: linux-media, aford, cphealy, kernel test robot, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

On Tue, Jan 25, 2022 at 11:11:24AM -0600, Adam Ford wrote:
> With the Hantro G1 and G2 now setup to run independently, update
> the device tree to allow both to operate.  This requires the
> vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> certain clock enabled to handle the gating of the G1 and G2
> fuses, the clock-parents and clock-rates for the various VPU's
> to be moved into the pgc_vpu because they cannot get re-parented
> once enabled, and the pgc_vpu is the highest in the chain.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reported-by: kernel test robot <lkp@intel.com>

It doesn't seem correct to have the Reported-by on this commit.

Thanks,
Ezequiel

> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 2df2510d0118..549b2440f55d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
>  					pgc_vpu: power-domain@6 {
>  						#power-domain-cells = <0>;
>  						reg = <IMX8M_POWER_DOMAIN_VPU>;
> -						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> +						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
> +							 <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> +							 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> +						assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> +								  <&clk IMX8MQ_CLK_VPU_G2>,
> +								  <&clk IMX8MQ_CLK_VPU_BUS>,
> +								  <&clk IMX8MQ_VPU_PLL_BYPASS>;
> +						assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> +									 <&clk IMX8MQ_VPU_PLL_OUT>,
> +									 <&clk IMX8MQ_SYS1_PLL_800M>,
> +									 <&clk IMX8MQ_VPU_PLL>;
> +						assigned-clock-rates = <600000000>,
> +								       <600000000>,
> +								       <800000000>,
> +								       <0>;
>  					};
>  
>  					pgc_disp: power-domain@7 {
> @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
>  			status = "disabled";
>  		};
>  
> -		vpu: video-codec@38300000 {
> -			compatible = "nxp,imx8mq-vpu";
> -			reg = <0x38300000 0x10000>,
> -			      <0x38310000 0x10000>,
> -			      <0x38320000 0x10000>;
> -			reg-names = "g1", "g2", "ctrl";
> -			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "g1", "g2";
> +		vpu_g1: video-codec@38300000 {
> +			compatible = "nxp,imx8mq-vpu-g1";
> +			reg = <0x38300000 0x10000>;
> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> +			power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> +		};
> +
> +		vpu_g2: video-codec@38310000 {
> +			compatible = "nxp,imx8mq-vpu-g2";
> +			reg = <0x38310000 0x10000>;
> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> +			power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> +		};
> +
> +		vpu_blk_ctrl: blk-ctrl@38320000 {
> +			compatible = "fsl,imx8mq-vpu-blk-ctrl";
> +			reg = <0x38320000 0x100>;
> +			power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
> +			power-domain-names = "bus", "g1", "g2";
>  			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> -				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> -				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> -			clock-names = "g1", "g2", "bus";
> -			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> -					  <&clk IMX8MQ_CLK_VPU_G2>,
> -					  <&clk IMX8MQ_CLK_VPU_BUS>,
> -					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
> -			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> -						 <&clk IMX8MQ_VPU_PLL_OUT>,
> -						 <&clk IMX8MQ_SYS1_PLL_800M>,
> -						 <&clk IMX8MQ_VPU_PLL>;
> -			assigned-clock-rates = <600000000>, <600000000>,
> -					       <800000000>, <0>;
> -			power-domains = <&pgc_vpu>;
> +				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> +			clock-names = "g1", "g2";
> +			#power-domain-cells = <1>;
>  		};
>  
>  		pcie0: pcie@33800000 {
> -- 
> 2.32.0
> 

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-01-25 19:04   ` Ezequiel Garcia
@ 2022-01-25 19:08     ` Adam Ford
  2022-02-09  7:27     ` Shawn Guo
  1 sibling, 0 replies; 44+ messages in thread
From: Adam Ford @ 2022-01-25 19:08 UTC (permalink / raw)
  To: Ezequiel Garcia
  Cc: linux-media, Adam Ford-BE, Chris Healy, kernel test robot,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, Lucas Stach,
	open list:HANTRO VPU CODEC DRIVER, devicetree, arm-soc,
	Linux Kernel Mailing List, open list:STAGING SUBSYSTEM

On Tue, Jan 25, 2022 at 1:04 PM Ezequiel Garcia
<ezequiel@vanguardiasur.com.ar> wrote:
>
> On Tue, Jan 25, 2022 at 11:11:24AM -0600, Adam Ford wrote:
> > With the Hantro G1 and G2 now setup to run independently, update
> > the device tree to allow both to operate.  This requires the
> > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > certain clock enabled to handle the gating of the G1 and G2
> > fuses, the clock-parents and clock-rates for the various VPU's
> > to be moved into the pgc_vpu because they cannot get re-parented
> > once enabled, and the pgc_vpu is the highest in the chain.
> >
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> > Reported-by: kernel test robot <lkp@intel.com>
>
> It doesn't seem correct to have the Reported-by on this commit.

I didn't put it here, because I fixed it in a whole different patch
(Patch 1/11).  This patch remains unchanged.  I probably should have
put in the other patch, but I didn't think it was essential.  Sorry
about that. Do I need to resend to just add the r-b tag?

adam

>
> Thanks,
> Ezequiel
>
> > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 2df2510d0118..549b2440f55d 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> >                                       pgc_vpu: power-domain@6 {
> >                                               #power-domain-cells = <0>;
> >                                               reg = <IMX8M_POWER_DOMAIN_VPU>;
> > -                                             clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > +                                             clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
> > +                                                      <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > +                                                      <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > +                                             assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> > +                                                               <&clk IMX8MQ_CLK_VPU_G2>,
> > +                                                               <&clk IMX8MQ_CLK_VPU_BUS>,
> > +                                                               <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > +                                             assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > +                                                                      <&clk IMX8MQ_VPU_PLL_OUT>,
> > +                                                                      <&clk IMX8MQ_SYS1_PLL_800M>,
> > +                                                                      <&clk IMX8MQ_VPU_PLL>;
> > +                                             assigned-clock-rates = <600000000>,
> > +                                                                    <600000000>,
> > +                                                                    <800000000>,
> > +                                                                    <0>;
> >                                       };
> >
> >                                       pgc_disp: power-domain@7 {
> > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> >                       status = "disabled";
> >               };
> >
> > -             vpu: video-codec@38300000 {
> > -                     compatible = "nxp,imx8mq-vpu";
> > -                     reg = <0x38300000 0x10000>,
> > -                           <0x38310000 0x10000>,
> > -                           <0x38320000 0x10000>;
> > -                     reg-names = "g1", "g2", "ctrl";
> > -                     interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > -                                  <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > -                     interrupt-names = "g1", "g2";
> > +             vpu_g1: video-codec@38300000 {
> > +                     compatible = "nxp,imx8mq-vpu-g1";
> > +                     reg = <0x38300000 0x10000>;
> > +                     interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > +                     clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> > +                     power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> > +             };
> > +
> > +             vpu_g2: video-codec@38310000 {
> > +                     compatible = "nxp,imx8mq-vpu-g2";
> > +                     reg = <0x38310000 0x10000>;
> > +                     interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > +                     clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > +                     power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> > +             };
> > +
> > +             vpu_blk_ctrl: blk-ctrl@38320000 {
> > +                     compatible = "fsl,imx8mq-vpu-blk-ctrl";
> > +                     reg = <0x38320000 0x100>;
> > +                     power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
> > +                     power-domain-names = "bus", "g1", "g2";
> >                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > -                              <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > -                              <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > -                     clock-names = "g1", "g2", "bus";
> > -                     assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> > -                                       <&clk IMX8MQ_CLK_VPU_G2>,
> > -                                       <&clk IMX8MQ_CLK_VPU_BUS>,
> > -                                       <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > -                     assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > -                                              <&clk IMX8MQ_VPU_PLL_OUT>,
> > -                                              <&clk IMX8MQ_SYS1_PLL_800M>,
> > -                                              <&clk IMX8MQ_VPU_PLL>;
> > -                     assigned-clock-rates = <600000000>, <600000000>,
> > -                                            <800000000>, <0>;
> > -                     power-domains = <&pgc_vpu>;
> > +                              <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > +                     clock-names = "g1", "g2";
> > +                     #power-domain-cells = <1>;
> >               };
> >
> >               pcie0: pcie@33800000 {
> > --
> > 2.32.0
> >

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: (EXT) [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
  2022-01-25 17:11 ` [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference Adam Ford
  2022-01-25 18:22   ` Lucas Stach
  2022-01-25 18:57   ` Ezequiel Garcia
@ 2022-01-26  6:42   ` Alexander Stein
  2022-02-09  7:10   ` Shawn Guo
  3 siblings, 0 replies; 44+ messages in thread
From: Alexander Stein @ 2022-01-26  6:42 UTC (permalink / raw)
  To: Adam Ford
  Cc: linux-media, aford, cphealy, Adam Ford, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, Lucas Stach, linux-rockchip,
	devicetree, linux-arm-kernel, linux-kernel, linux-staging

Am Dienstag, 25. Januar 2022, 18:11:18 CET schrieb Adam Ford:
> The vpu is enabled by default, so there is no need to manually
> enable it.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi index
> 8aedcddfeab8..38ffcd145b33 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
> @@ -272,10 +272,6 @@ &usdhc1 {
>  	status = "okay";
>  };
> 
> -&vpu {
> -	status = "okay";
> -};
> -
>  /* Attention: wdog reset forcing POR needs baseboard support */
>  &wdog1 {
>  	status = "okay";





^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: (EXT) [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm
  2022-01-25 17:11 ` [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm Adam Ford
@ 2022-01-26  6:45   ` Alexander Stein
  2022-02-04 23:16   ` Rob Herring
  1 sibling, 0 replies; 44+ messages in thread
From: Alexander Stein @ 2022-01-26  6:45 UTC (permalink / raw)
  To: Adam Ford
  Cc: linux-media, aford, cphealy, Adam Ford, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, Lucas Stach, linux-rockchip,
	devicetree, linux-arm-kernel, linux-kernel, linux-staging

Am Dienstag, 25. Januar 2022, 18:11:26 CET schrieb Adam Ford:
> The i.MX8M mini appears to have a similar G1 decoder but the
> post-processing isn't present, so different compatible flag is required.
> Since all the other parameters are the same with imx8mq, just add
> the new compatible flag to nxp,imx8mq-vpu.yaml.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> 
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml index
> 9c28d562112b..7dc13a4b1805 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> @@ -5,7 +5,7 @@
>  $id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#"
>  $schema: "http://devicetree.org/meta-schemas/core.yaml#"
> 
> -title: Hantro G1/G2 VPU codecs implemented on i.MX8MQ SoCs
> +title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs
> 
>  maintainers:
>    - Philipp Zabel <p.zabel@pengutronix.de>
> @@ -20,6 +20,7 @@ properties:
>          deprecated: true
>        - const: nxp,imx8mq-vpu-g1
>        - const: nxp,imx8mq-vpu-g2
> +      - const: nxp,imx8mm-vpu-g1
> 
>    reg:
>      maxItems: 1

Is there no rule that items are sorted alphabetically?

Regards,
Alexander





^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
  2022-01-25 17:11 ` [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains Adam Ford
@ 2022-01-27  8:46   ` Hans Verkuil
  2022-02-03 13:16     ` Adam Ford
  2022-02-05 14:01     ` Ezequiel Garcia
  2022-02-09  7:14   ` Shawn Guo
  1 sibling, 2 replies; 44+ messages in thread
From: Hans Verkuil @ 2022-01-27  8:46 UTC (permalink / raw)
  To: Shawn Guo
  Cc: aford, cphealy, Lucas Stach, Rob Herring, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, linux-rockchip, devicetree, linux-arm-kernel,
	linux-kernel, linux-staging, linux-media, Adam Ford

Shawn,

Can you take patches 2-4 of this series or shall I? In the latter case I
need your Acked-by for these three patches.

Regards,

	Hans

On 25/01/2022 18:11, Adam Ford wrote:
> From: Lucas Stach <l.stach@pengutronix.de>
> 
> This adds the defines for the power domains provided by the VPU
> blk-ctrl on the i.MX8MQ.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Acked-by: Rob Herring <robh@kernel.org>
> 
> diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h
> index 8a513bd9166e..9f7d0f1e7c32 100644
> --- a/include/dt-bindings/power/imx8mq-power.h
> +++ b/include/dt-bindings/power/imx8mq-power.h
> @@ -18,4 +18,7 @@
>  #define IMX8M_POWER_DOMAIN_MIPI_CSI2	9
>  #define IMX8M_POWER_DOMAIN_PCIE2	10
>  
> +#define IMX8MQ_VPUBLK_PD_G1		0
> +#define IMX8MQ_VPUBLK_PD_G2		1
> +
>  #endif


^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
  2022-01-27  8:46   ` Hans Verkuil
@ 2022-02-03 13:16     ` Adam Ford
  2022-02-05 14:01     ` Ezequiel Garcia
  1 sibling, 0 replies; 44+ messages in thread
From: Adam Ford @ 2022-02-03 13:16 UTC (permalink / raw)
  To: Hans Verkuil
  Cc: Shawn Guo, Adam Ford-BE, Chris Healy, Lucas Stach, Rob Herring,
	Ezequiel Garcia, Philipp Zabel, Mauro Carvalho Chehab,
	Rob Herring, Sascha Hauer, Pengutronix Kernel Team,
	Fabio Estevam, NXP Linux Team, Greg Kroah-Hartman,
	open list:HANTRO VPU CODEC DRIVER, devicetree, arm-soc,
	Linux Kernel Mailing List, open list:STAGING SUBSYSTEM,
	linux-media

On Thu, Jan 27, 2022 at 2:46 AM Hans Verkuil <hverkuil@xs4all.nl> wrote:
>
> Shawn,
>
> Can you take patches 2-4 of this series or shall I? In the latter case I
> need your Acked-by for these three patches.

If necessary, I can tweak the YAML file.  I just need to know if I
need to resubmit the whole series of just the one file.

adam
>
> Regards,
>
>         Hans
>
> On 25/01/2022 18:11, Adam Ford wrote:
> > From: Lucas Stach <l.stach@pengutronix.de>
> >
> > This adds the defines for the power domains provided by the VPU
> > blk-ctrl on the i.MX8MQ.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Acked-by: Rob Herring <robh@kernel.org>
> >
> > diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h
> > index 8a513bd9166e..9f7d0f1e7c32 100644
> > --- a/include/dt-bindings/power/imx8mq-power.h
> > +++ b/include/dt-bindings/power/imx8mq-power.h
> > @@ -18,4 +18,7 @@
> >  #define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
> >  #define IMX8M_POWER_DOMAIN_PCIE2     10
> >
> > +#define IMX8MQ_VPUBLK_PD_G1          0
> > +#define IMX8MQ_VPUBLK_PD_G2          1
> > +
> >  #endif
>

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm
  2022-01-25 17:11 ` [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm Adam Ford
  2022-01-26  6:45   ` (EXT) " Alexander Stein
@ 2022-02-04 23:16   ` Rob Herring
  1 sibling, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-02-04 23:16 UTC (permalink / raw)
  To: Adam Ford
  Cc: Fabio Estevam, Shawn Guo, linux-staging, linux-kernel,
	linux-rockchip, aford, NXP Linux Team, Philipp Zabel,
	Rob Herring, linux-arm-kernel, Greg Kroah-Hartman,
	Ezequiel Garcia, Pengutronix Kernel Team, Lucas Stach,
	Mauro Carvalho Chehab, Sascha Hauer, devicetree, cphealy,
	linux-media

On Tue, 25 Jan 2022 11:11:26 -0600, Adam Ford wrote:
> The i.MX8M mini appears to have a similar G1 decoder but the
> post-processing isn't present, so different compatible flag is required.
> Since all the other parameters are the same with imx8mq, just add
> the new compatible flag to nxp,imx8mq-vpu.yaml.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
  2022-01-27  8:46   ` Hans Verkuil
  2022-02-03 13:16     ` Adam Ford
@ 2022-02-05 14:01     ` Ezequiel Garcia
  1 sibling, 0 replies; 44+ messages in thread
From: Ezequiel Garcia @ 2022-02-05 14:01 UTC (permalink / raw)
  To: Hans Verkuil
  Cc: Shawn Guo, Adam Ford-BE, Chris Healy, Lucas Stach, Rob Herring,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, open list:ARM/Rockchip SoC...,
	devicetree, linux-arm-kernel, Linux Kernel Mailing List,
	open list:STAGING SUBSYSTEM, linux-media, Adam Ford

Hi Shawn, Hans,

On Thu, 27 Jan 2022 at 05:46, Hans Verkuil <hverkuil@xs4all.nl> wrote:
>
> Shawn,
>
> Can you take patches 2-4 of this series or shall I? In the latter case I
> need your Acked-by for these three patches.
>

Gentle reminder about these patches.

Thanks!
Ezequiel


> Regards,
>
>         Hans
>
> On 25/01/2022 18:11, Adam Ford wrote:
> > From: Lucas Stach <l.stach@pengutronix.de>
> >
> > This adds the defines for the power domains provided by the VPU
> > blk-ctrl on the i.MX8MQ.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Acked-by: Rob Herring <robh@kernel.org>
> >
> > diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h
> > index 8a513bd9166e..9f7d0f1e7c32 100644
> > --- a/include/dt-bindings/power/imx8mq-power.h
> > +++ b/include/dt-bindings/power/imx8mq-power.h
> > @@ -18,4 +18,7 @@
> >  #define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
> >  #define IMX8M_POWER_DOMAIN_PCIE2     10
> >
> > +#define IMX8MQ_VPUBLK_PD_G1          0
> > +#define IMX8MQ_VPUBLK_PD_G2          1
> > +
> >  #endif
>

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
  2022-01-25 17:11 ` [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference Adam Ford
                     ` (2 preceding siblings ...)
  2022-01-26  6:42   ` (EXT) " Alexander Stein
@ 2022-02-09  7:10   ` Shawn Guo
  3 siblings, 0 replies; 44+ messages in thread
From: Shawn Guo @ 2022-02-09  7:10 UTC (permalink / raw)
  To: Adam Ford
  Cc: linux-media, aford, cphealy, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

On Tue, Jan 25, 2022 at 11:11:18AM -0600, Adam Ford wrote:
> The vpu is enabled by default, so there is no need to manually
> enable it.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Applied, thanks!

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
  2022-01-25 17:11 ` [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains Adam Ford
  2022-01-27  8:46   ` Hans Verkuil
@ 2022-02-09  7:14   ` Shawn Guo
  1 sibling, 0 replies; 44+ messages in thread
From: Shawn Guo @ 2022-02-09  7:14 UTC (permalink / raw)
  To: Adam Ford
  Cc: linux-media, aford, cphealy, Lucas Stach, Rob Herring,
	Ezequiel Garcia, Philipp Zabel, Mauro Carvalho Chehab,
	Rob Herring, Sascha Hauer, Pengutronix Kernel Team,
	Fabio Estevam, NXP Linux Team, Greg Kroah-Hartman,
	linux-rockchip, devicetree, linux-arm-kernel, linux-kernel,
	linux-staging

On Tue, Jan 25, 2022 at 11:11:19AM -0600, Adam Ford wrote:
> From: Lucas Stach <l.stach@pengutronix.de>
> 
> This adds the defines for the power domains provided by the VPU
> blk-ctrl on the i.MX8MQ.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Acked-by: Rob Herring <robh@kernel.org>

When forwarding a patch from someone else, you should add your
Signed-off-by.

Applied, thanks!

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 03/11] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl
  2022-01-25 17:11 ` [PATCH V4 03/11] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl Adam Ford
@ 2022-02-09  7:16   ` Shawn Guo
  0 siblings, 0 replies; 44+ messages in thread
From: Shawn Guo @ 2022-02-09  7:16 UTC (permalink / raw)
  To: Adam Ford
  Cc: linux-media, aford, cphealy, Lucas Stach, Rob Herring,
	Ezequiel Garcia, Philipp Zabel, Mauro Carvalho Chehab,
	Rob Herring, Sascha Hauer, Pengutronix Kernel Team,
	Fabio Estevam, NXP Linux Team, Greg Kroah-Hartman,
	linux-rockchip, devicetree, linux-arm-kernel, linux-kernel,
	linux-staging

On Tue, Jan 25, 2022 at 11:11:20AM -0600, Adam Ford wrote:
> From: Lucas Stach <l.stach@pengutronix.de>
> 
> This adds the DT binding for the i.MX8MQ VPU blk-ctrl.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Rob Herring <robh@kernel.org>

Applied, thanks!

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 04/11] soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl
  2022-01-25 17:11 ` [PATCH V4 04/11] soc: imx: imx8m-blk-ctrl: add " Adam Ford
@ 2022-02-09  7:19   ` Shawn Guo
  0 siblings, 0 replies; 44+ messages in thread
From: Shawn Guo @ 2022-02-09  7:19 UTC (permalink / raw)
  To: Adam Ford
  Cc: linux-media, aford, cphealy, Lucas Stach, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, linux-rockchip, devicetree, linux-arm-kernel,
	linux-kernel, linux-staging

On Tue, Jan 25, 2022 at 11:11:21AM -0600, Adam Ford wrote:
> From: Lucas Stach <l.stach@pengutronix.de>
> 
> This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to
> avoid putting more of this functionality into the decoder driver.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Signed-off-by: Adam Ford <aford173@gmail.com>

Applied, thanks!

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-01-25 19:04   ` Ezequiel Garcia
  2022-01-25 19:08     ` Adam Ford
@ 2022-02-09  7:27     ` Shawn Guo
  1 sibling, 0 replies; 44+ messages in thread
From: Shawn Guo @ 2022-02-09  7:27 UTC (permalink / raw)
  To: Ezequiel Garcia
  Cc: Adam Ford, linux-media, aford, cphealy, kernel test robot,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

On Tue, Jan 25, 2022 at 04:04:38PM -0300, Ezequiel Garcia wrote:
> On Tue, Jan 25, 2022 at 11:11:24AM -0600, Adam Ford wrote:
> > With the Hantro G1 and G2 now setup to run independently, update
> > the device tree to allow both to operate.  This requires the
> > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > certain clock enabled to handle the gating of the G1 and G2
> > fuses, the clock-parents and clock-rates for the various VPU's
> > to be moved into the pgc_vpu because they cannot get re-parented
> > once enabled, and the pgc_vpu is the highest in the chain.
> > 
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> > Reported-by: kernel test robot <lkp@intel.com>
> 
> It doesn't seem correct to have the Reported-by on this commit.

Applied with Reported-by tag dropped, thanks!

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging
  2022-01-25 17:11 ` [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging Adam Ford
  2022-01-25 18:19   ` Lucas Stach
@ 2022-02-09  7:33   ` Shawn Guo
  1 sibling, 0 replies; 44+ messages in thread
From: Shawn Guo @ 2022-02-09  7:33 UTC (permalink / raw)
  To: Adam Ford
  Cc: linux-media, aford, cphealy, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

On Tue, Jan 25, 2022 at 11:11:25AM -0600, Adam Ford wrote:
> The vpumix power domain has a reset assigned to it, however
> when used, it causes a system hang.  Testing has shown that
> it does not appear to be needed anywhere.
> 
> Fixes: d39d4bb15310 ("arm64: dts: imx8mm: add GPC node")
> Signed-off-by: Adam Ford <aford173@gmail.com>

Applied, thanks!

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders
  2022-01-25 17:11 ` [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders Adam Ford
  2022-01-25 18:21   ` Lucas Stach
@ 2022-02-09  7:35   ` Shawn Guo
  1 sibling, 0 replies; 44+ messages in thread
From: Shawn Guo @ 2022-02-09  7:35 UTC (permalink / raw)
  To: Adam Ford
  Cc: linux-media, aford, cphealy, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, Lucas Stach, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

On Tue, Jan 25, 2022 at 11:11:28AM -0600, Adam Ford wrote:
> There are two decoders on the i.MX8M Mini controlled by the
> vpu-blk-ctrl.  The G1 supports H264 and VP8 while the
> G2 support HEVC and VP9.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Applied, thanks!

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-01-25 17:11 ` [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Adam Ford
  2022-01-25 18:20   ` Lucas Stach
  2022-01-25 19:04   ` Ezequiel Garcia
@ 2022-04-25 15:22   ` Martin Kepplinger
  2022-04-25 15:34     ` Lucas Stach
  2 siblings, 1 reply; 44+ messages in thread
From: Martin Kepplinger @ 2022-04-25 15:22 UTC (permalink / raw)
  To: Adam Ford, linux-media
  Cc: aford, cphealy, kernel test robot, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, Lucas Stach, linux-rockchip,
	devicetree, linux-arm-kernel, linux-kernel, linux-staging

Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> With the Hantro G1 and G2 now setup to run independently, update
> the device tree to allow both to operate.  This requires the
> vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> certain clock enabled to handle the gating of the G1 and G2
> fuses, the clock-parents and clock-rates for the various VPU's
> to be moved into the pgc_vpu because they cannot get re-parented
> once enabled, and the pgc_vpu is the highest in the chain.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reported-by: kernel test robot <lkp@intel.com>
> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 2df2510d0118..549b2440f55d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
>                                         pgc_vpu: power-domain@6 {
>                                                 #power-domain-cells =
> <0>;
>                                                 reg =
> <IMX8M_POWER_DOMAIN_VPU>;
> -                                               clocks = <&clk
> IMX8MQ_CLK_VPU_DEC_ROOT>;
> +                                               clocks = <&clk
> IMX8MQ_CLK_VPU_DEC_ROOT>,
> +                                                        <&clk
> IMX8MQ_CLK_VPU_G1_ROOT>,
> +                                                        <&clk
> IMX8MQ_CLK_VPU_G2_ROOT>;
> +                                               assigned-clocks =
> <&clk IMX8MQ_CLK_VPU_G1>,
> +                                                                
> <&clk IMX8MQ_CLK_VPU_G2>,
> +                                                                
> <&clk IMX8MQ_CLK_VPU_BUS>,
> +                                                                
> <&clk IMX8MQ_VPU_PLL_BYPASS>;
> +                                               assigned-clock-
> parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> +                                                                    
>     <&clk IMX8MQ_VPU_PLL_OUT>,
> +                                                                    
>     <&clk IMX8MQ_SYS1_PLL_800M>,
> +                                                                    
>     <&clk IMX8MQ_VPU_PLL>;
> +                                               assigned-clock-rates
> = <600000000>,
> +                                                                    
>   <600000000>,
> +                                                                    
>   <800000000>,
> +                                                                    
>   <0>;
>                                         };
>  
>                                         pgc_disp: power-domain@7 {
> @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
>                         status = "disabled";
>                 };
>  
> -               vpu: video-codec@38300000 {
> -                       compatible = "nxp,imx8mq-vpu";
> -                       reg = <0x38300000 0x10000>,
> -                             <0x38310000 0x10000>,
> -                             <0x38320000 0x10000>;
> -                       reg-names = "g1", "g2", "ctrl";
> -                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> -                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> -                       interrupt-names = "g1", "g2";
> +               vpu_g1: video-codec@38300000 {
> +                       compatible = "nxp,imx8mq-vpu-g1";
> +                       reg = <0x38300000 0x10000>;
> +                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> +                       power-domains = <&vpu_blk_ctrl
> IMX8MQ_VPUBLK_PD_G1>;
> +               };
> +
> +               vpu_g2: video-codec@38310000 {
> +                       compatible = "nxp,imx8mq-vpu-g2";
> +                       reg = <0x38310000 0x10000>;
> +                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> +                       power-domains = <&vpu_blk_ctrl
> IMX8MQ_VPUBLK_PD_G2>;
> +               };
> +
> +               vpu_blk_ctrl: blk-ctrl@38320000 {
> +                       compatible = "fsl,imx8mq-vpu-blk-ctrl";
> +                       reg = <0x38320000 0x100>;
> +                       power-domains = <&pgc_vpu>, <&pgc_vpu>,
> <&pgc_vpu>;
> +                       power-domain-names = "bus", "g1", "g2";
>                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> -                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> -                                <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> -                       clock-names = "g1", "g2", "bus";
> -                       assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> -                                         <&clk IMX8MQ_CLK_VPU_G2>,
> -                                         <&clk IMX8MQ_CLK_VPU_BUS>,
> -                                         <&clk
> IMX8MQ_VPU_PLL_BYPASS>;
> -                       assigned-clock-parents = <&clk
> IMX8MQ_VPU_PLL_OUT>,
> -                                                <&clk
> IMX8MQ_VPU_PLL_OUT>,
> -                                                <&clk
> IMX8MQ_SYS1_PLL_800M>,
> -                                                <&clk
> IMX8MQ_VPU_PLL>;
> -                       assigned-clock-rates = <600000000>,
> <600000000>,
> -                                              <800000000>, <0>;
> -                       power-domains = <&pgc_vpu>;
> +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> +                       clock-names = "g1", "g2";
> +                       #power-domain-cells = <1>;
>                 };
>  
>                 pcie0: pcie@33800000 {

With this update, when testing suspend to ram on imx8mq, I get:

buck4: failed to disable: -ETIMEDOUT

where buck4 is power-supply of pgc_vpu. And thus the transition to
suspend (and resuming) fails.

Have you tested system suspend after the imx8m-blk-ctrl update on
imx8mq?

thank you,

                                 martin


^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-04-25 15:22   ` Martin Kepplinger
@ 2022-04-25 15:34     ` Lucas Stach
  2022-04-25 15:47       ` Adam Ford
  2022-04-26  7:38       ` Martin Kepplinger
  0 siblings, 2 replies; 44+ messages in thread
From: Lucas Stach @ 2022-04-25 15:34 UTC (permalink / raw)
  To: Martin Kepplinger, Adam Ford, linux-media
  Cc: aford, cphealy, kernel test robot, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

Hi Martin,

Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin Kepplinger:
> Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > With the Hantro G1 and G2 now setup to run independently, update
> > the device tree to allow both to operate.  This requires the
> > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > certain clock enabled to handle the gating of the G1 and G2
> > fuses, the clock-parents and clock-rates for the various VPU's
> > to be moved into the pgc_vpu because they cannot get re-parented
> > once enabled, and the pgc_vpu is the highest in the chain.
> > 
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> > Reported-by: kernel test robot <lkp@intel.com>
> > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 2df2510d0118..549b2440f55d 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> >                                         pgc_vpu: power-domain@6 {
> >                                                 #power-domain-cells =
> > <0>;
> >                                                 reg =
> > <IMX8M_POWER_DOMAIN_VPU>;
> > -                                               clocks = <&clk
> > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > +                                               clocks = <&clk
> > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > +                                                        <&clk
> > IMX8MQ_CLK_VPU_G1_ROOT>,
> > +                                                        <&clk
> > IMX8MQ_CLK_VPU_G2_ROOT>;
> > +                                               assigned-clocks =
> > <&clk IMX8MQ_CLK_VPU_G1>,
> > +                                                                
> > <&clk IMX8MQ_CLK_VPU_G2>,
> > +                                                                
> > <&clk IMX8MQ_CLK_VPU_BUS>,
> > +                                                                
> > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > +                                               assigned-clock-
> > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > +                                                                    
> >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > +                                                                    
> >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > +                                                                    
> >     <&clk IMX8MQ_VPU_PLL>;
> > +                                               assigned-clock-rates
> > = <600000000>,
> > +                                                                    
> >   <600000000>,
> > +                                                                    
> >   <800000000>,
> > +                                                                    
> >   <0>;
> >                                         };
> >  
> >                                         pgc_disp: power-domain@7 {
> > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> >                         status = "disabled";
> >                 };
> >  
> > -               vpu: video-codec@38300000 {
> > -                       compatible = "nxp,imx8mq-vpu";
> > -                       reg = <0x38300000 0x10000>,
> > -                             <0x38310000 0x10000>,
> > -                             <0x38320000 0x10000>;
> > -                       reg-names = "g1", "g2", "ctrl";
> > -                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > -                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > -                       interrupt-names = "g1", "g2";
> > +               vpu_g1: video-codec@38300000 {
> > +                       compatible = "nxp,imx8mq-vpu-g1";
> > +                       reg = <0x38300000 0x10000>;
> > +                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> > +                       power-domains = <&vpu_blk_ctrl
> > IMX8MQ_VPUBLK_PD_G1>;
> > +               };
> > +
> > +               vpu_g2: video-codec@38310000 {
> > +                       compatible = "nxp,imx8mq-vpu-g2";
> > +                       reg = <0x38310000 0x10000>;
> > +                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > +                       power-domains = <&vpu_blk_ctrl
> > IMX8MQ_VPUBLK_PD_G2>;
> > +               };
> > +
> > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > +                       compatible = "fsl,imx8mq-vpu-blk-ctrl";
> > +                       reg = <0x38320000 0x100>;
> > +                       power-domains = <&pgc_vpu>, <&pgc_vpu>,
> > <&pgc_vpu>;
> > +                       power-domain-names = "bus", "g1", "g2";
> >                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > -                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > -                                <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > -                       clock-names = "g1", "g2", "bus";
> > -                       assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> > -                                         <&clk IMX8MQ_CLK_VPU_G2>,
> > -                                         <&clk IMX8MQ_CLK_VPU_BUS>,
> > -                                         <&clk
> > IMX8MQ_VPU_PLL_BYPASS>;
> > -                       assigned-clock-parents = <&clk
> > IMX8MQ_VPU_PLL_OUT>,
> > -                                                <&clk
> > IMX8MQ_VPU_PLL_OUT>,
> > -                                                <&clk
> > IMX8MQ_SYS1_PLL_800M>,
> > -                                                <&clk
> > IMX8MQ_VPU_PLL>;
> > -                       assigned-clock-rates = <600000000>,
> > <600000000>,
> > -                                              <800000000>, <0>;
> > -                       power-domains = <&pgc_vpu>;
> > +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > +                       clock-names = "g1", "g2";
> > +                       #power-domain-cells = <1>;
> >                 };
> >  
> >                 pcie0: pcie@33800000 {
> 
> With this update, when testing suspend to ram on imx8mq, I get:
> 
> buck4: failed to disable: -ETIMEDOUT
> 
> where buck4 is power-supply of pgc_vpu. And thus the transition to
> suspend (and resuming) fails.
> 
> Have you tested system suspend after the imx8m-blk-ctrl update on
> imx8mq?

I haven't tested system suspend, don't know if anyone else did. However
I guess that this is just uncovering a preexisting issue in the system
suspend sequencing, which you would also hit if the video decoders were
active at system suspend time.

My guess is that the regulator disable fails, due to the power domains
being disabled quite late in the suspend sequence, where i2c
communication with the PMIC is no longer possible due to i2c being
suspended already or something like that. Maybe you can dig in a bit on
the actual sequence on your system and we can see how we can rework
things to suspend the power domains at a time where communication with
the PMIC is still possible?

Regards,
Lucas


^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-04-25 15:34     ` Lucas Stach
@ 2022-04-25 15:47       ` Adam Ford
  2022-04-26 10:28         ` Martin Kepplinger
  2022-04-26  7:38       ` Martin Kepplinger
  1 sibling, 1 reply; 44+ messages in thread
From: Adam Ford @ 2022-04-25 15:47 UTC (permalink / raw)
  To: Lucas Stach
  Cc: Martin Kepplinger, linux-media, Adam Ford-BE, Chris Healy,
	kernel test robot, Ezequiel Garcia, Philipp Zabel,
	Mauro Carvalho Chehab, Rob Herring, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	Greg Kroah-Hartman, open list:HANTRO VPU CODEC DRIVER,
	devicetree, arm-soc, Linux Kernel Mailing List,
	open list:STAGING SUBSYSTEM

On Mon, Apr 25, 2022 at 10:34 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Hi Martin,
>
> Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin Kepplinger:
> > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > With the Hantro G1 and G2 now setup to run independently, update
> > > the device tree to allow both to operate.  This requires the
> > > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > > certain clock enabled to handle the gating of the G1 and G2
> > > fuses, the clock-parents and clock-rates for the various VPU's
> > > to be moved into the pgc_vpu because they cannot get re-parented
> > > once enabled, and the pgc_vpu is the highest in the chain.
> > >
> > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > Reported-by: kernel test robot <lkp@intel.com>
> > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > index 2df2510d0118..549b2440f55d 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > >                                         pgc_vpu: power-domain@6 {
> > >                                                 #power-domain-cells =
> > > <0>;
> > >                                                 reg =
> > > <IMX8M_POWER_DOMAIN_VPU>;
> > > -                                               clocks = <&clk
> > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > +                                               clocks = <&clk
> > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > +                                                        <&clk
> > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > +                                                        <&clk
> > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > +                                               assigned-clocks =
> > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > +
> > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > +
> > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > +
> > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > +                                               assigned-clock-
> > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > +
> > >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > > +
> > >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > > +
> > >     <&clk IMX8MQ_VPU_PLL>;
> > > +                                               assigned-clock-rates
> > > = <600000000>,
> > > +
> > >   <600000000>,
> > > +
> > >   <800000000>,
> > > +
> > >   <0>;
> > >                                         };
> > >
> > >                                         pgc_disp: power-domain@7 {
> > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > >                         status = "disabled";
> > >                 };
> > >
> > > -               vpu: video-codec@38300000 {
> > > -                       compatible = "nxp,imx8mq-vpu";
> > > -                       reg = <0x38300000 0x10000>,
> > > -                             <0x38310000 0x10000>,
> > > -                             <0x38320000 0x10000>;
> > > -                       reg-names = "g1", "g2", "ctrl";
> > > -                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > > -                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > > -                       interrupt-names = "g1", "g2";
> > > +               vpu_g1: video-codec@38300000 {
> > > +                       compatible = "nxp,imx8mq-vpu-g1";
> > > +                       reg = <0x38300000 0x10000>;
> > > +                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > > +                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> > > +                       power-domains = <&vpu_blk_ctrl
> > > IMX8MQ_VPUBLK_PD_G1>;
> > > +               };
> > > +
> > > +               vpu_g2: video-codec@38310000 {
> > > +                       compatible = "nxp,imx8mq-vpu-g2";
> > > +                       reg = <0x38310000 0x10000>;
> > > +                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > > +                       clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > +                       power-domains = <&vpu_blk_ctrl
> > > IMX8MQ_VPUBLK_PD_G2>;
> > > +               };
> > > +
> > > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > > +                       compatible = "fsl,imx8mq-vpu-blk-ctrl";
> > > +                       reg = <0x38320000 0x100>;
> > > +                       power-domains = <&pgc_vpu>, <&pgc_vpu>,
> > > <&pgc_vpu>;
> > > +                       power-domain-names = "bus", "g1", "g2";
> > >                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > > -                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > > -                                <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > -                       clock-names = "g1", "g2", "bus";
> > > -                       assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> > > -                                         <&clk IMX8MQ_CLK_VPU_G2>,
> > > -                                         <&clk IMX8MQ_CLK_VPU_BUS>,
> > > -                                         <&clk
> > > IMX8MQ_VPU_PLL_BYPASS>;
> > > -                       assigned-clock-parents = <&clk
> > > IMX8MQ_VPU_PLL_OUT>,
> > > -                                                <&clk
> > > IMX8MQ_VPU_PLL_OUT>,
> > > -                                                <&clk
> > > IMX8MQ_SYS1_PLL_800M>,
> > > -                                                <&clk
> > > IMX8MQ_VPU_PLL>;
> > > -                       assigned-clock-rates = <600000000>,
> > > <600000000>,
> > > -                                              <800000000>, <0>;
> > > -                       power-domains = <&pgc_vpu>;
> > > +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > +                       clock-names = "g1", "g2";
> > > +                       #power-domain-cells = <1>;
> > >                 };
> > >
> > >                 pcie0: pcie@33800000 {
> >
> > With this update, when testing suspend to ram on imx8mq, I get:
> >
> > buck4: failed to disable: -ETIMEDOUT
> >
> > where buck4 is power-supply of pgc_vpu. And thus the transition to
> > suspend (and resuming) fails.
> >
> > Have you tested system suspend after the imx8m-blk-ctrl update on
> > imx8mq?
>
> I haven't tested system suspend, don't know if anyone else did. However
> I guess that this is just uncovering a preexisting issue in the system
> suspend sequencing, which you would also hit if the video decoders were
> active at system suspend time.

I have not tested it either.

>
> My guess is that the regulator disable fails, due to the power domains
> being disabled quite late in the suspend sequence, where i2c
> communication with the PMIC is no longer possible due to i2c being
> suspended already or something like that. Maybe you can dig in a bit on
> the actual sequence on your system and we can see how we can rework
> things to suspend the power domains at a time where communication with
> the PMIC is still possible?

In the meantime, should we mark the regulator with regulator-always-on
so it doesn't attempt to power it down?  It might not be ideal,but it
might be enough to let it suspend.

adam
>
> Regards,
> Lucas
>

^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-04-25 15:34     ` Lucas Stach
  2022-04-25 15:47       ` Adam Ford
@ 2022-04-26  7:38       ` Martin Kepplinger
  2022-04-26 10:43         ` Lucas Stach
  1 sibling, 1 reply; 44+ messages in thread
From: Martin Kepplinger @ 2022-04-26  7:38 UTC (permalink / raw)
  To: Lucas Stach, Adam Ford, linux-media
  Cc: aford, cphealy, kernel test robot, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

Am Montag, dem 25.04.2022 um 17:34 +0200 schrieb Lucas Stach:
> Hi Martin,
> 
> Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin Kepplinger:
> > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > With the Hantro G1 and G2 now setup to run independently, update
> > > the device tree to allow both to operate.  This requires the
> > > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > > certain clock enabled to handle the gating of the G1 and G2
> > > fuses, the clock-parents and clock-rates for the various VPU's
> > > to be moved into the pgc_vpu because they cannot get re-parented
> > > once enabled, and the pgc_vpu is the highest in the chain.
> > > 
> > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > Reported-by: kernel test robot <lkp@intel.com>
> > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > > 
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > index 2df2510d0118..549b2440f55d 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > >                                         pgc_vpu: power-domain@6 {
> > >                                                 #power-domain-
> > > cells =
> > > <0>;
> > >                                                 reg =
> > > <IMX8M_POWER_DOMAIN_VPU>;
> > > -                                               clocks = <&clk
> > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > +                                               clocks = <&clk
> > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > +                                                        <&clk
> > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > +                                                        <&clk
> > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > +                                               assigned-clocks =
> > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > +                                                                
> > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > +                                                                
> > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > +                                                                
> > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > +                                               assigned-clock-
> > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > +                                                                
> > >     
> > >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > > +                                                                
> > >     
> > >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > > +                                                                
> > >     
> > >     <&clk IMX8MQ_VPU_PLL>;
> > > +                                               assigned-clock-
> > > rates
> > > = <600000000>,
> > > +                                                                
> > >     
> > >   <600000000>,
> > > +                                                                
> > >     
> > >   <800000000>,
> > > +                                                                
> > >     
> > >   <0>;
> > >                                         };
> > >  
> > >                                         pgc_disp: power-domain@7
> > > {
> > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > >                         status = "disabled";
> > >                 };
> > >  
> > > -               vpu: video-codec@38300000 {
> > > -                       compatible = "nxp,imx8mq-vpu";
> > > -                       reg = <0x38300000 0x10000>,
> > > -                             <0x38310000 0x10000>,
> > > -                             <0x38320000 0x10000>;
> > > -                       reg-names = "g1", "g2", "ctrl";
> > > -                       interrupts = <GIC_SPI 7
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > -                                    <GIC_SPI 8
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > -                       interrupt-names = "g1", "g2";
> > > +               vpu_g1: video-codec@38300000 {
> > > +                       compatible = "nxp,imx8mq-vpu-g1";
> > > +                       reg = <0x38300000 0x10000>;
> > > +                       interrupts = <GIC_SPI 7
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > +                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> > > +                       power-domains = <&vpu_blk_ctrl
> > > IMX8MQ_VPUBLK_PD_G1>;
> > > +               };
> > > +
> > > +               vpu_g2: video-codec@38310000 {
> > > +                       compatible = "nxp,imx8mq-vpu-g2";
> > > +                       reg = <0x38310000 0x10000>;
> > > +                       interrupts = <GIC_SPI 8
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > +                       clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > +                       power-domains = <&vpu_blk_ctrl
> > > IMX8MQ_VPUBLK_PD_G2>;
> > > +               };
> > > +
> > > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > > +                       compatible = "fsl,imx8mq-vpu-blk-ctrl";
> > > +                       reg = <0x38320000 0x100>;
> > > +                       power-domains = <&pgc_vpu>, <&pgc_vpu>,
> > > <&pgc_vpu>;
> > > +                       power-domain-names = "bus", "g1", "g2";
> > >                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > > -                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > > -                                <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > -                       clock-names = "g1", "g2", "bus";
> > > -                       assigned-clocks = <&clk
> > > IMX8MQ_CLK_VPU_G1>,
> > > -                                         <&clk
> > > IMX8MQ_CLK_VPU_G2>,
> > > -                                         <&clk
> > > IMX8MQ_CLK_VPU_BUS>,
> > > -                                         <&clk
> > > IMX8MQ_VPU_PLL_BYPASS>;
> > > -                       assigned-clock-parents = <&clk
> > > IMX8MQ_VPU_PLL_OUT>,
> > > -                                                <&clk
> > > IMX8MQ_VPU_PLL_OUT>,
> > > -                                                <&clk
> > > IMX8MQ_SYS1_PLL_800M>,
> > > -                                                <&clk
> > > IMX8MQ_VPU_PLL>;
> > > -                       assigned-clock-rates = <600000000>,
> > > <600000000>,
> > > -                                              <800000000>, <0>;
> > > -                       power-domains = <&pgc_vpu>;
> > > +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > +                       clock-names = "g1", "g2";
> > > +                       #power-domain-cells = <1>;
> > >                 };
> > >  
> > >                 pcie0: pcie@33800000 {
> > 
> > With this update, when testing suspend to ram on imx8mq, I get:
> > 
> > buck4: failed to disable: -ETIMEDOUT
> > 
> > where buck4 is power-supply of pgc_vpu. And thus the transition to
> > suspend (and resuming) fails.
> > 
> > Have you tested system suspend after the imx8m-blk-ctrl update on
> > imx8mq?
> 
> I haven't tested system suspend, don't know if anyone else did.
> However
> I guess that this is just uncovering a preexisting issue in the
> system
> suspend sequencing, which you would also hit if the video decoders
> were
> active at system suspend time.
> 
> My guess is that the regulator disable fails, due to the power
> domains
> being disabled quite late in the suspend sequence, where i2c
> communication with the PMIC is no longer possible due to i2c being
> suspended already or something like that. Maybe you can dig in a bit
> on
> the actual sequence on your system and we can see how we can rework
> things to suspend the power domains at a time where communication
> with
> the PMIC is still possible?

What exactly would you like to see? Here's all gpcv2 regulators
disabling on suspend. (gpu (domain 5) is disabled by runtime pm often):

[   47.138700] imx-pgc imx-pgc-domain.5: disabling regulator
[   47.298071] Freezing user space processes ... (elapsed 0.008
seconds) done.
[   47.313432] OOM killer disabled.
[   47.316670] Freezing remaining freezable tasks ... (elapsed 2.221
seconds) done.
[   49.672052] imx8m-blk-ctrl 38320000.blk-ctrl: imx8m_blk_ctrl_suspend
start
[   49.704417] imx-pgc imx-pgc-domain.0: disabling regulator
[   49.711114] imx-pgc imx-pgc-domain.6: disabling regulator
[   49.819064] buck4: failed to disable: -ETIMEDOUT

The stack looks pretty much the same for all of them, from pm_suspend()
over genpd_suspend_noiry().

And as a reminder, power-domain nr 0=mipi, 5=gpu, 6=vpu.

> 
> Regards,
> Lucas
> 



^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-04-25 15:47       ` Adam Ford
@ 2022-04-26 10:28         ` Martin Kepplinger
  2022-04-26 10:40           ` Lucas Stach
  0 siblings, 1 reply; 44+ messages in thread
From: Martin Kepplinger @ 2022-04-26 10:28 UTC (permalink / raw)
  To: Adam Ford, Lucas Stach
  Cc: linux-media, Adam Ford-BE, Chris Healy, kernel test robot,
	Ezequiel Garcia, Philipp Zabel, Mauro Carvalho Chehab,
	Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
	Fabio Estevam, NXP Linux Team, Greg Kroah-Hartman,
	open list:HANTRO VPU CODEC DRIVER, devicetree, arm-soc,
	Linux Kernel Mailing List, open list:STAGING SUBSYSTEM

Am Montag, dem 25.04.2022 um 10:47 -0500 schrieb Adam Ford:
> On Mon, Apr 25, 2022 at 10:34 AM Lucas Stach <l.stach@pengutronix.de>
> wrote:
> > 
> > Hi Martin,
> > 
> > Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin Kepplinger:
> > > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > > With the Hantro G1 and G2 now setup to run independently,
> > > > update
> > > > the device tree to allow both to operate.  This requires the
> > > > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > > > certain clock enabled to handle the gating of the G1 and G2
> > > > fuses, the clock-parents and clock-rates for the various VPU's
> > > > to be moved into the pgc_vpu because they cannot get re-
> > > > parented
> > > > once enabled, and the pgc_vpu is the highest in the chain.
> > > > 
> > > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > > Reported-by: kernel test robot <lkp@intel.com>
> > > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > > > 
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > index 2df2510d0118..549b2440f55d 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > > >                                         pgc_vpu: power-domain@6
> > > > {
> > > >                                                 #power-domain-
> > > > cells =
> > > > <0>;
> > > >                                                 reg =
> > > > <IMX8M_POWER_DOMAIN_VPU>;
> > > > -                                               clocks = <&clk
> > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > +                                               clocks = <&clk
> > > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > > +                                                        <&clk
> > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > +                                                        <&clk
> > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > +                                               assigned-clocks
> > > > =
> > > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > > +
> > > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > > +
> > > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > > +
> > > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > > +                                               assigned-clock-
> > > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > +
> > > >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > +
> > > >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > > > +
> > > >     <&clk IMX8MQ_VPU_PLL>;
> > > > +                                               assigned-clock-
> > > > rates
> > > > = <600000000>,
> > > > +
> > > >   <600000000>,
> > > > +
> > > >   <800000000>,
> > > > +
> > > >   <0>;
> > > >                                         };
> > > > 
> > > >                                         pgc_disp: power-
> > > > domain@7 {
> > > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > > >                         status = "disabled";
> > > >                 };
> > > > 
> > > > -               vpu: video-codec@38300000 {
> > > > -                       compatible = "nxp,imx8mq-vpu";
> > > > -                       reg = <0x38300000 0x10000>,
> > > > -                             <0x38310000 0x10000>,
> > > > -                             <0x38320000 0x10000>;
> > > > -                       reg-names = "g1", "g2", "ctrl";
> > > > -                       interrupts = <GIC_SPI 7
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > -                                    <GIC_SPI 8
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > -                       interrupt-names = "g1", "g2";
> > > > +               vpu_g1: video-codec@38300000 {
> > > > +                       compatible = "nxp,imx8mq-vpu-g1";
> > > > +                       reg = <0x38300000 0x10000>;
> > > > +                       interrupts = <GIC_SPI 7
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > +                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> > > > +                       power-domains = <&vpu_blk_ctrl
> > > > IMX8MQ_VPUBLK_PD_G1>;
> > > > +               };
> > > > +
> > > > +               vpu_g2: video-codec@38310000 {
> > > > +                       compatible = "nxp,imx8mq-vpu-g2";
> > > > +                       reg = <0x38310000 0x10000>;
> > > > +                       interrupts = <GIC_SPI 8
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > +                       clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > +                       power-domains = <&vpu_blk_ctrl
> > > > IMX8MQ_VPUBLK_PD_G2>;
> > > > +               };
> > > > +
> > > > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > > > +                       compatible = "fsl,imx8mq-vpu-blk-ctrl";
> > > > +                       reg = <0x38320000 0x100>;
> > > > +                       power-domains = <&pgc_vpu>, <&pgc_vpu>,
> > > > <&pgc_vpu>;
> > > > +                       power-domain-names = "bus", "g1", "g2";
> > > >                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > -                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > > > -                                <&clk
> > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > -                       clock-names = "g1", "g2", "bus";
> > > > -                       assigned-clocks = <&clk
> > > > IMX8MQ_CLK_VPU_G1>,
> > > > -                                         <&clk
> > > > IMX8MQ_CLK_VPU_G2>,
> > > > -                                         <&clk
> > > > IMX8MQ_CLK_VPU_BUS>,
> > > > -                                         <&clk
> > > > IMX8MQ_VPU_PLL_BYPASS>;
> > > > -                       assigned-clock-parents = <&clk
> > > > IMX8MQ_VPU_PLL_OUT>,
> > > > -                                                <&clk
> > > > IMX8MQ_VPU_PLL_OUT>,
> > > > -                                                <&clk
> > > > IMX8MQ_SYS1_PLL_800M>,
> > > > -                                                <&clk
> > > > IMX8MQ_VPU_PLL>;
> > > > -                       assigned-clock-rates = <600000000>,
> > > > <600000000>,
> > > > -                                              <800000000>,
> > > > <0>;
> > > > -                       power-domains = <&pgc_vpu>;
> > > > +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > +                       clock-names = "g1", "g2";
> > > > +                       #power-domain-cells = <1>;
> > > >                 };
> > > > 
> > > >                 pcie0: pcie@33800000 {
> > > 
> > > With this update, when testing suspend to ram on imx8mq, I get:
> > > 
> > > buck4: failed to disable: -ETIMEDOUT
> > > 
> > > where buck4 is power-supply of pgc_vpu. And thus the transition
> > > to
> > > suspend (and resuming) fails.
> > > 
> > > Have you tested system suspend after the imx8m-blk-ctrl update on
> > > imx8mq?
> > 
> > I haven't tested system suspend, don't know if anyone else did.
> > However
> > I guess that this is just uncovering a preexisting issue in the
> > system
> > suspend sequencing, which you would also hit if the video decoders
> > were
> > active at system suspend time.
> 
> I have not tested it either.
> 
> > 
> > My guess is that the regulator disable fails, due to the power
> > domains
> > being disabled quite late in the suspend sequence, where i2c
> > communication with the PMIC is no longer possible due to i2c being
> > suspended already or something like that. Maybe you can dig in a
> > bit on
> > the actual sequence on your system and we can see how we can rework
> > things to suspend the power domains at a time where communication
> > with
> > the PMIC is still possible?
> 
> In the meantime, should we mark the regulator with regulator-always-
> on
> so it doesn't attempt to power it down?  It might not be ideal,but it
> might be enough to let it suspend.
> 

it would be a temporary workaround, but I want to remind you that it
wouldn't help much: even if suspending "works" again, system resume is
broken on imx8mq since
https://lore.kernel.org/all/a20ecd639f8e8b7fa4a9bed7a8e9590225262784.camel@puri.sm/

Of course I did the current tests on v5.18-rc4 without any gpcv2
changes to mainline. But for resume to work I need the one revert from
the above link (plus a minor additional hack) already.

If we'd have that working in mainline I could make sure it stays that
way :)

                           martin



^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-04-26 10:28         ` Martin Kepplinger
@ 2022-04-26 10:40           ` Lucas Stach
  0 siblings, 0 replies; 44+ messages in thread
From: Lucas Stach @ 2022-04-26 10:40 UTC (permalink / raw)
  To: Martin Kepplinger, Adam Ford
  Cc: linux-media, Adam Ford-BE, Chris Healy, kernel test robot,
	Ezequiel Garcia, Philipp Zabel, Mauro Carvalho Chehab,
	Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
	Fabio Estevam, NXP Linux Team, Greg Kroah-Hartman,
	open list:HANTRO VPU CODEC DRIVER, devicetree, arm-soc,
	Linux Kernel Mailing List, open list:STAGING SUBSYSTEM

Am Dienstag, dem 26.04.2022 um 12:28 +0200 schrieb Martin Kepplinger:
> Am Montag, dem 25.04.2022 um 10:47 -0500 schrieb Adam Ford:
> > On Mon, Apr 25, 2022 at 10:34 AM Lucas Stach <l.stach@pengutronix.de>
> > wrote:
> > > 
> > > Hi Martin,
> > > 
> > > Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin Kepplinger:
> > > > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > > > With the Hantro G1 and G2 now setup to run independently,
> > > > > update
> > > > > the device tree to allow both to operate.  This requires the
> > > > > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > > > > certain clock enabled to handle the gating of the G1 and G2
> > > > > fuses, the clock-parents and clock-rates for the various VPU's
> > > > > to be moved into the pgc_vpu because they cannot get re-
> > > > > parented
> > > > > once enabled, and the pgc_vpu is the highest in the chain.
> > > > > 
> > > > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > > > Reported-by: kernel test robot <lkp@intel.com>
> > > > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > index 2df2510d0118..549b2440f55d 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > > > >                                         pgc_vpu: power-domain@6
> > > > > {
> > > > >                                                 #power-domain-
> > > > > cells =
> > > > > <0>;
> > > > >                                                 reg =
> > > > > <IMX8M_POWER_DOMAIN_VPU>;
> > > > > -                                               clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > +                                               clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > > > +                                                        <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > +                                                        <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                                               assigned-clocks
> > > > > =
> > > > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > > > +
> > > > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > > > +
> > > > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > > > +
> > > > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > > > +                                               assigned-clock-
> > > > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +
> > > > >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +
> > > > >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > > > > +
> > > > >     <&clk IMX8MQ_VPU_PLL>;
> > > > > +                                               assigned-clock-
> > > > > rates
> > > > > = <600000000>,
> > > > > +
> > > > >   <600000000>,
> > > > > +
> > > > >   <800000000>,
> > > > > +
> > > > >   <0>;
> > > > >                                         };
> > > > > 
> > > > >                                         pgc_disp: power-
> > > > > domain@7 {
> > > > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > > > >                         status = "disabled";
> > > > >                 };
> > > > > 
> > > > > -               vpu: video-codec@38300000 {
> > > > > -                       compatible = "nxp,imx8mq-vpu";
> > > > > -                       reg = <0x38300000 0x10000>,
> > > > > -                             <0x38310000 0x10000>,
> > > > > -                             <0x38320000 0x10000>;
> > > > > -                       reg-names = "g1", "g2", "ctrl";
> > > > > -                       interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > -                                    <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > -                       interrupt-names = "g1", "g2";
> > > > > +               vpu_g1: video-codec@38300000 {
> > > > > +                       compatible = "nxp,imx8mq-vpu-g1";
> > > > > +                       reg = <0x38300000 0x10000>;
> > > > > +                       interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G1>;
> > > > > +               };
> > > > > +
> > > > > +               vpu_g2: video-codec@38310000 {
> > > > > +                       compatible = "nxp,imx8mq-vpu-g2";
> > > > > +                       reg = <0x38310000 0x10000>;
> > > > > +                       interrupts = <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G2>;
> > > > > +               };
> > > > > +
> > > > > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > > > > +                       compatible = "fsl,imx8mq-vpu-blk-ctrl";
> > > > > +                       reg = <0x38320000 0x100>;
> > > > > +                       power-domains = <&pgc_vpu>, <&pgc_vpu>,
> > > > > <&pgc_vpu>;
> > > > > +                       power-domain-names = "bus", "g1", "g2";
> > > > >                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > -                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > > > > -                                <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > -                       clock-names = "g1", "g2", "bus";
> > > > > -                       assigned-clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_CLK_VPU_G2>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_CLK_VPU_BUS>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_VPU_PLL_BYPASS>;
> > > > > -                       assigned-clock-parents = <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_SYS1_PLL_800M>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_VPU_PLL>;
> > > > > -                       assigned-clock-rates = <600000000>,
> > > > > <600000000>,
> > > > > -                                              <800000000>,
> > > > > <0>;
> > > > > -                       power-domains = <&pgc_vpu>;
> > > > > +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                       clock-names = "g1", "g2";
> > > > > +                       #power-domain-cells = <1>;
> > > > >                 };
> > > > > 
> > > > >                 pcie0: pcie@33800000 {
> > > > 
> > > > With this update, when testing suspend to ram on imx8mq, I get:
> > > > 
> > > > buck4: failed to disable: -ETIMEDOUT
> > > > 
> > > > where buck4 is power-supply of pgc_vpu. And thus the transition
> > > > to
> > > > suspend (and resuming) fails.
> > > > 
> > > > Have you tested system suspend after the imx8m-blk-ctrl update on
> > > > imx8mq?
> > > 
> > > I haven't tested system suspend, don't know if anyone else did.
> > > However
> > > I guess that this is just uncovering a preexisting issue in the
> > > system
> > > suspend sequencing, which you would also hit if the video decoders
> > > were
> > > active at system suspend time.
> > 
> > I have not tested it either.
> > 
> > > 
> > > My guess is that the regulator disable fails, due to the power
> > > domains
> > > being disabled quite late in the suspend sequence, where i2c
> > > communication with the PMIC is no longer possible due to i2c being
> > > suspended already or something like that. Maybe you can dig in a
> > > bit on
> > > the actual sequence on your system and we can see how we can rework
> > > things to suspend the power domains at a time where communication
> > > with
> > > the PMIC is still possible?
> > 
> > In the meantime, should we mark the regulator with regulator-always-
> > on
> > so it doesn't attempt to power it down?  It might not be ideal,but it
> > might be enough to let it suspend.
> > 
> 
> it would be a temporary workaround, but I want to remind you that it
> wouldn't help much: even if suspending "works" again, system resume is
> broken on imx8mq since
> https://lore.kernel.org/all/a20ecd639f8e8b7fa4a9bed7a8e9590225262784.camel@puri.sm/
> 
> Of course I did the current tests on v5.18-rc4 without any gpcv2
> changes to mainline. But for resume to work I need the one revert from
> the above link (plus a minor additional hack) already.
> 
> If we'd have that working in mainline I could make sure it stays that
> way :)
> 
This looks like the same underlying issue to me. We need to suspend the
power domains before i2c (or whatever is causing the regulator disable
fail) and only resume them after this subsystem is resumed.

Regards,
Lucas



^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-04-26  7:38       ` Martin Kepplinger
@ 2022-04-26 10:43         ` Lucas Stach
  2022-04-26 12:12           ` Martin Kepplinger
                             ` (3 more replies)
  0 siblings, 4 replies; 44+ messages in thread
From: Lucas Stach @ 2022-04-26 10:43 UTC (permalink / raw)
  To: Martin Kepplinger, Adam Ford, linux-media
  Cc: aford, cphealy, kernel test robot, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

Am Dienstag, dem 26.04.2022 um 09:38 +0200 schrieb Martin Kepplinger:
> Am Montag, dem 25.04.2022 um 17:34 +0200 schrieb Lucas Stach:
> > Hi Martin,
> > 
> > Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin Kepplinger:
> > > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > > With the Hantro G1 and G2 now setup to run independently, update
> > > > the device tree to allow both to operate.  This requires the
> > > > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > > > certain clock enabled to handle the gating of the G1 and G2
> > > > fuses, the clock-parents and clock-rates for the various VPU's
> > > > to be moved into the pgc_vpu because they cannot get re-parented
> > > > once enabled, and the pgc_vpu is the highest in the chain.
> > > > 
> > > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > > Reported-by: kernel test robot <lkp@intel.com>
> > > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > > > 
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > index 2df2510d0118..549b2440f55d 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > > >                                         pgc_vpu: power-domain@6 {
> > > >                                                 #power-domain-
> > > > cells =
> > > > <0>;
> > > >                                                 reg =
> > > > <IMX8M_POWER_DOMAIN_VPU>;
> > > > -                                               clocks = <&clk
> > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > +                                               clocks = <&clk
> > > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > > +                                                        <&clk
> > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > +                                                        <&clk
> > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > +                                               assigned-clocks =
> > > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > > +                                                                
> > > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > > +                                                                
> > > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > > +                                                                
> > > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > > +                                               assigned-clock-
> > > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > +                                                                
> > > >     
> > > >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > +                                                                
> > > >     
> > > >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > > > +                                                                
> > > >     
> > > >     <&clk IMX8MQ_VPU_PLL>;
> > > > +                                               assigned-clock-
> > > > rates
> > > > = <600000000>,
> > > > +                                                                
> > > >     
> > > >   <600000000>,
> > > > +                                                                
> > > >     
> > > >   <800000000>,
> > > > +                                                                
> > > >     
> > > >   <0>;
> > > >                                         };
> > > >  
> > > >                                         pgc_disp: power-domain@7
> > > > {
> > > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > > >                         status = "disabled";
> > > >                 };
> > > >  
> > > > -               vpu: video-codec@38300000 {
> > > > -                       compatible = "nxp,imx8mq-vpu";
> > > > -                       reg = <0x38300000 0x10000>,
> > > > -                             <0x38310000 0x10000>,
> > > > -                             <0x38320000 0x10000>;
> > > > -                       reg-names = "g1", "g2", "ctrl";
> > > > -                       interrupts = <GIC_SPI 7
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > -                                    <GIC_SPI 8
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > -                       interrupt-names = "g1", "g2";
> > > > +               vpu_g1: video-codec@38300000 {
> > > > +                       compatible = "nxp,imx8mq-vpu-g1";
> > > > +                       reg = <0x38300000 0x10000>;
> > > > +                       interrupts = <GIC_SPI 7
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > +                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> > > > +                       power-domains = <&vpu_blk_ctrl
> > > > IMX8MQ_VPUBLK_PD_G1>;
> > > > +               };
> > > > +
> > > > +               vpu_g2: video-codec@38310000 {
> > > > +                       compatible = "nxp,imx8mq-vpu-g2";
> > > > +                       reg = <0x38310000 0x10000>;
> > > > +                       interrupts = <GIC_SPI 8
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > +                       clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > +                       power-domains = <&vpu_blk_ctrl
> > > > IMX8MQ_VPUBLK_PD_G2>;
> > > > +               };
> > > > +
> > > > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > > > +                       compatible = "fsl,imx8mq-vpu-blk-ctrl";
> > > > +                       reg = <0x38320000 0x100>;
> > > > +                       power-domains = <&pgc_vpu>, <&pgc_vpu>,
> > > > <&pgc_vpu>;
> > > > +                       power-domain-names = "bus", "g1", "g2";
> > > >                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > -                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > > > -                                <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > -                       clock-names = "g1", "g2", "bus";
> > > > -                       assigned-clocks = <&clk
> > > > IMX8MQ_CLK_VPU_G1>,
> > > > -                                         <&clk
> > > > IMX8MQ_CLK_VPU_G2>,
> > > > -                                         <&clk
> > > > IMX8MQ_CLK_VPU_BUS>,
> > > > -                                         <&clk
> > > > IMX8MQ_VPU_PLL_BYPASS>;
> > > > -                       assigned-clock-parents = <&clk
> > > > IMX8MQ_VPU_PLL_OUT>,
> > > > -                                                <&clk
> > > > IMX8MQ_VPU_PLL_OUT>,
> > > > -                                                <&clk
> > > > IMX8MQ_SYS1_PLL_800M>,
> > > > -                                                <&clk
> > > > IMX8MQ_VPU_PLL>;
> > > > -                       assigned-clock-rates = <600000000>,
> > > > <600000000>,
> > > > -                                              <800000000>, <0>;
> > > > -                       power-domains = <&pgc_vpu>;
> > > > +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > +                       clock-names = "g1", "g2";
> > > > +                       #power-domain-cells = <1>;
> > > >                 };
> > > >  
> > > >                 pcie0: pcie@33800000 {
> > > 
> > > With this update, when testing suspend to ram on imx8mq, I get:
> > > 
> > > buck4: failed to disable: -ETIMEDOUT
> > > 
> > > where buck4 is power-supply of pgc_vpu. And thus the transition to
> > > suspend (and resuming) fails.
> > > 
> > > Have you tested system suspend after the imx8m-blk-ctrl update on
> > > imx8mq?
> > 
> > I haven't tested system suspend, don't know if anyone else did.
> > However
> > I guess that this is just uncovering a preexisting issue in the
> > system
> > suspend sequencing, which you would also hit if the video decoders
> > were
> > active at system suspend time.
> > 
> > My guess is that the regulator disable fails, due to the power
> > domains
> > being disabled quite late in the suspend sequence, where i2c
> > communication with the PMIC is no longer possible due to i2c being
> > suspended already or something like that. Maybe you can dig in a bit
> > on
> > the actual sequence on your system and we can see how we can rework
> > things to suspend the power domains at a time where communication
> > with
> > the PMIC is still possible?
> 
> What exactly would you like to see? Here's all gpcv2 regulators
> disabling on suspend. (gpu (domain 5) is disabled by runtime pm often):
> 
> [   47.138700] imx-pgc imx-pgc-domain.5: disabling regulator
> [   47.298071] Freezing user space processes ... (elapsed 0.008
> seconds) done.
> [   47.313432] OOM killer disabled.
> [   47.316670] Freezing remaining freezable tasks ... (elapsed 2.221
> seconds) done.
> [   49.672052] imx8m-blk-ctrl 38320000.blk-ctrl: imx8m_blk_ctrl_suspend
> start
> [   49.704417] imx-pgc imx-pgc-domain.0: disabling regulator
> [   49.711114] imx-pgc imx-pgc-domain.6: disabling regulator
> [   49.819064] buck4: failed to disable: -ETIMEDOUT
> 
> The stack looks pretty much the same for all of them, from pm_suspend()
> over genpd_suspend_noiry().

So the GPU domain is already suspended before the system suspend,
probably due to short runtime PM timeouts.

Can you please check at which point the i2c subsystem is suspended? I
think we are already past that point when running the PM domain suspend
from a _noirq callback. I'll take a look on how we can properly change
this ordering.

Regards,
Lucas


^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-04-26 10:43         ` Lucas Stach
@ 2022-04-26 12:12           ` Martin Kepplinger
  2022-04-29  9:52           ` Martin Kepplinger
                             ` (2 subsequent siblings)
  3 siblings, 0 replies; 44+ messages in thread
From: Martin Kepplinger @ 2022-04-26 12:12 UTC (permalink / raw)
  To: Lucas Stach, Adam Ford, linux-media
  Cc: aford, cphealy, kernel test robot, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

Am Dienstag, dem 26.04.2022 um 12:43 +0200 schrieb Lucas Stach:
> Am Dienstag, dem 26.04.2022 um 09:38 +0200 schrieb Martin Kepplinger:
> > Am Montag, dem 25.04.2022 um 17:34 +0200 schrieb Lucas Stach:
> > > Hi Martin,
> > > 
> > > Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin
> > > Kepplinger:
> > > > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > > > With the Hantro G1 and G2 now setup to run independently,
> > > > > update
> > > > > the device tree to allow both to operate.  This requires the
> > > > > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > > > > certain clock enabled to handle the gating of the G1 and G2
> > > > > fuses, the clock-parents and clock-rates for the various
> > > > > VPU's
> > > > > to be moved into the pgc_vpu because they cannot get re-
> > > > > parented
> > > > > once enabled, and the pgc_vpu is the highest in the chain.
> > > > > 
> > > > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > > > Reported-by: kernel test robot <lkp@intel.com>
> > > > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > index 2df2510d0118..549b2440f55d 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > > > >                                         pgc_vpu: power-
> > > > > domain@6 {
> > > > >                                                 #power-
> > > > > domain-
> > > > > cells =
> > > > > <0>;
> > > > >                                                 reg =
> > > > > <IMX8M_POWER_DOMAIN_VPU>;
> > > > > -                                               clocks =
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > +                                               clocks =
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > > > +                                                       
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > +                                                       
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                                               assigned-
> > > > > clocks =
> > > > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > > > +                                               assigned-
> > > > > clock-
> > > > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_VPU_PLL>;
> > > > > +                                               assigned-
> > > > > clock-
> > > > > rates
> > > > > = <600000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <600000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <800000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <0>;
> > > > >                                         };
> > > > >  
> > > > >                                         pgc_disp:
> > > > > power-domain@7
> > > > > {
> > > > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > > > >                         status = "disabled";
> > > > >                 };
> > > > >  
> > > > > -               vpu: video-codec@38300000 {
> > > > > -                       compatible = "nxp,imx8mq-vpu";
> > > > > -                       reg = <0x38300000 0x10000>,
> > > > > -                             <0x38310000 0x10000>,
> > > > > -                             <0x38320000 0x10000>;
> > > > > -                       reg-names = "g1", "g2", "ctrl";
> > > > > -                       interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > -                                    <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > -                       interrupt-names = "g1", "g2";
> > > > > +               vpu_g1: video-codec@38300000 {
> > > > > +                       compatible = "nxp,imx8mq-vpu-g1";
> > > > > +                       reg = <0x38300000 0x10000>;
> > > > > +                       interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>;
> > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G1>;
> > > > > +               };
> > > > > +
> > > > > +               vpu_g2: video-codec@38310000 {
> > > > > +                       compatible = "nxp,imx8mq-vpu-g2";
> > > > > +                       reg = <0x38310000 0x10000>;
> > > > > +                       interrupts = <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G2>;
> > > > > +               };
> > > > > +
> > > > > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > > > > +                       compatible = "fsl,imx8mq-vpu-blk-
> > > > > ctrl";
> > > > > +                       reg = <0x38320000 0x100>;
> > > > > +                       power-domains = <&pgc_vpu>,
> > > > > <&pgc_vpu>,
> > > > > <&pgc_vpu>;
> > > > > +                       power-domain-names = "bus", "g1",
> > > > > "g2";
> > > > >                         clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > -                                <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>,
> > > > > -                                <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > -                       clock-names = "g1", "g2", "bus";
> > > > > -                       assigned-clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_CLK_VPU_G2>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_CLK_VPU_BUS>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_VPU_PLL_BYPASS>;
> > > > > -                       assigned-clock-parents = <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_SYS1_PLL_800M>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_VPU_PLL>;
> > > > > -                       assigned-clock-rates = <600000000>,
> > > > > <600000000>,
> > > > > -                                              <800000000>,
> > > > > <0>;
> > > > > -                       power-domains = <&pgc_vpu>;
> > > > > +                                <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                       clock-names = "g1", "g2";
> > > > > +                       #power-domain-cells = <1>;
> > > > >                 };
> > > > >  
> > > > >                 pcie0: pcie@33800000 {
> > > > 
> > > > With this update, when testing suspend to ram on imx8mq, I get:
> > > > 
> > > > buck4: failed to disable: -ETIMEDOUT
> > > > 
> > > > where buck4 is power-supply of pgc_vpu. And thus the transition
> > > > to
> > > > suspend (and resuming) fails.
> > > > 
> > > > Have you tested system suspend after the imx8m-blk-ctrl update
> > > > on
> > > > imx8mq?
> > > 
> > > I haven't tested system suspend, don't know if anyone else did.
> > > However
> > > I guess that this is just uncovering a preexisting issue in the
> > > system
> > > suspend sequencing, which you would also hit if the video
> > > decoders
> > > were
> > > active at system suspend time.
> > > 
> > > My guess is that the regulator disable fails, due to the power
> > > domains
> > > being disabled quite late in the suspend sequence, where i2c
> > > communication with the PMIC is no longer possible due to i2c
> > > being
> > > suspended already or something like that. Maybe you can dig in a
> > > bit
> > > on
> > > the actual sequence on your system and we can see how we can
> > > rework
> > > things to suspend the power domains at a time where communication
> > > with
> > > the PMIC is still possible?
> > 
> > What exactly would you like to see? Here's all gpcv2 regulators
> > disabling on suspend. (gpu (domain 5) is disabled by runtime pm
> > often):
> > 
> > [   47.138700] imx-pgc imx-pgc-domain.5: disabling regulator
> > [   47.298071] Freezing user space processes ... (elapsed 0.008
> > seconds) done.
> > [   47.313432] OOM killer disabled.
> > [   47.316670] Freezing remaining freezable tasks ... (elapsed
> > 2.221
> > seconds) done.
> > [   49.672052] imx8m-blk-ctrl 38320000.blk-ctrl:
> > imx8m_blk_ctrl_suspend
> > start
> > [   49.704417] imx-pgc imx-pgc-domain.0: disabling regulator
> > [   49.711114] imx-pgc imx-pgc-domain.6: disabling regulator
> > [   49.819064] buck4: failed to disable: -ETIMEDOUT
> > 
> > The stack looks pretty much the same for all of them, from
> > pm_suspend()
> > over genpd_suspend_noiry().
> 
> So the GPU domain is already suspended before the system suspend,
> probably due to short runtime PM timeouts.
> 
> Can you please check at which point the i2c subsystem is suspended? I
> think we are already past that point when running the PM domain
> suspend
> from a _noirq callback. I'll take a look on how we can properly
> change
> this ordering.
> 
> Regards,
> Lucas
> 

not sure whether I correctly check that, but the last
i2c_imx_runtime_suspend() (here for i2c1 and i2c3) are executed before
the power-domain disable, so that makes sense(?):

[   40.774853] imx-pgc imx-pgc-domain.5: disable regulator now
[   40.786211] imx-i2c 30a20000.i2c: i2c_imx_runtime_suspend
[   40.910189] imx-i2c 30a40000.i2c: i2c_imx_runtime_suspend
[   40.940895] Freezing user space processes ... 
[   40.968914] rfkill: input handler enabled
[   40.979955] (elapsed 0.007 seconds) done.
[   40.984033] OOM killer disabled.
[   40.987297] Freezing remaining freezable tasks ... (elapsed 0.001
seconds) done.
[   41.264683] imx-pgc imx-pgc-domain.0: disable regulator now
[   41.271679] imx-pgc imx-pgc-domain.6: disable regulator now
[   41.378759] buck4: failed to disable: -ETIMEDOUT
[   41.383405] imx-pgc imx-pgc-domain.6: failed to disable regulator: -
110

And you can see that I have the domain.0 regulator set to always-on.
Otherwise it would time out as well in this case:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi#n900

thank a lot for taking the time to look at this!

                        martin



^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-04-26 10:43         ` Lucas Stach
  2022-04-26 12:12           ` Martin Kepplinger
@ 2022-04-29  9:52           ` Martin Kepplinger
  2022-05-23 12:00           ` Martin Kepplinger
  2022-07-11  9:53           ` Martin Kepplinger
  3 siblings, 0 replies; 44+ messages in thread
From: Martin Kepplinger @ 2022-04-29  9:52 UTC (permalink / raw)
  To: Lucas Stach, Adam Ford, linux-media
  Cc: aford, cphealy, kernel test robot, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

Am Dienstag, dem 26.04.2022 um 12:43 +0200 schrieb Lucas Stach:
> Am Dienstag, dem 26.04.2022 um 09:38 +0200 schrieb Martin Kepplinger:
> > Am Montag, dem 25.04.2022 um 17:34 +0200 schrieb Lucas Stach:
> > > Hi Martin,
> > > 
> > > Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin
> > > Kepplinger:
> > > > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > > > With the Hantro G1 and G2 now setup to run independently,
> > > > > update
> > > > > the device tree to allow both to operate.  This requires the
> > > > > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > > > > certain clock enabled to handle the gating of the G1 and G2
> > > > > fuses, the clock-parents and clock-rates for the various
> > > > > VPU's
> > > > > to be moved into the pgc_vpu because they cannot get re-
> > > > > parented
> > > > > once enabled, and the pgc_vpu is the highest in the chain.
> > > > > 
> > > > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > > > Reported-by: kernel test robot <lkp@intel.com>
> > > > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > index 2df2510d0118..549b2440f55d 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > > > >                                         pgc_vpu: power-
> > > > > domain@6 {
> > > > >                                                 #power-
> > > > > domain-
> > > > > cells =
> > > > > <0>;
> > > > >                                                 reg =
> > > > > <IMX8M_POWER_DOMAIN_VPU>;
> > > > > -                                               clocks =
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > +                                               clocks =
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > > > +                                                       
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > +                                                       
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                                               assigned-
> > > > > clocks =
> > > > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > > > +                                               assigned-
> > > > > clock-
> > > > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_VPU_PLL>;
> > > > > +                                               assigned-
> > > > > clock-
> > > > > rates
> > > > > = <600000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <600000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <800000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <0>;
> > > > >                                         };
> > > > >  
> > > > >                                         pgc_disp:
> > > > > power-domain@7
> > > > > {
> > > > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > > > >                         status = "disabled";
> > > > >                 };
> > > > >  
> > > > > -               vpu: video-codec@38300000 {
> > > > > -                       compatible = "nxp,imx8mq-vpu";
> > > > > -                       reg = <0x38300000 0x10000>,
> > > > > -                             <0x38310000 0x10000>,
> > > > > -                             <0x38320000 0x10000>;
> > > > > -                       reg-names = "g1", "g2", "ctrl";
> > > > > -                       interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > -                                    <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > -                       interrupt-names = "g1", "g2";
> > > > > +               vpu_g1: video-codec@38300000 {
> > > > > +                       compatible = "nxp,imx8mq-vpu-g1";
> > > > > +                       reg = <0x38300000 0x10000>;
> > > > > +                       interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>;
> > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G1>;
> > > > > +               };
> > > > > +
> > > > > +               vpu_g2: video-codec@38310000 {
> > > > > +                       compatible = "nxp,imx8mq-vpu-g2";
> > > > > +                       reg = <0x38310000 0x10000>;
> > > > > +                       interrupts = <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G2>;
> > > > > +               };
> > > > > +
> > > > > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > > > > +                       compatible = "fsl,imx8mq-vpu-blk-
> > > > > ctrl";
> > > > > +                       reg = <0x38320000 0x100>;
> > > > > +                       power-domains = <&pgc_vpu>,
> > > > > <&pgc_vpu>,
> > > > > <&pgc_vpu>;
> > > > > +                       power-domain-names = "bus", "g1",
> > > > > "g2";
> > > > >                         clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > -                                <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>,
> > > > > -                                <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > -                       clock-names = "g1", "g2", "bus";
> > > > > -                       assigned-clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_CLK_VPU_G2>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_CLK_VPU_BUS>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_VPU_PLL_BYPASS>;
> > > > > -                       assigned-clock-parents = <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_SYS1_PLL_800M>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_VPU_PLL>;
> > > > > -                       assigned-clock-rates = <600000000>,
> > > > > <600000000>,
> > > > > -                                              <800000000>,
> > > > > <0>;
> > > > > -                       power-domains = <&pgc_vpu>;
> > > > > +                                <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                       clock-names = "g1", "g2";
> > > > > +                       #power-domain-cells = <1>;
> > > > >                 };
> > > > >  
> > > > >                 pcie0: pcie@33800000 {
> > > > 
> > > > With this update, when testing suspend to ram on imx8mq, I get:
> > > > 
> > > > buck4: failed to disable: -ETIMEDOUT
> > > > 
> > > > where buck4 is power-supply of pgc_vpu. And thus the transition
> > > > to
> > > > suspend (and resuming) fails.
> > > > 
> > > > Have you tested system suspend after the imx8m-blk-ctrl update
> > > > on
> > > > imx8mq?
> > > 
> > > I haven't tested system suspend, don't know if anyone else did.
> > > However
> > > I guess that this is just uncovering a preexisting issue in the
> > > system
> > > suspend sequencing, which you would also hit if the video
> > > decoders
> > > were
> > > active at system suspend time.
> > > 
> > > My guess is that the regulator disable fails, due to the power
> > > domains
> > > being disabled quite late in the suspend sequence, where i2c
> > > communication with the PMIC is no longer possible due to i2c
> > > being
> > > suspended already or something like that. Maybe you can dig in a
> > > bit
> > > on
> > > the actual sequence on your system and we can see how we can
> > > rework
> > > things to suspend the power domains at a time where communication
> > > with
> > > the PMIC is still possible?
> > 
> > What exactly would you like to see? Here's all gpcv2 regulators
> > disabling on suspend. (gpu (domain 5) is disabled by runtime pm
> > often):
> > 
> > [   47.138700] imx-pgc imx-pgc-domain.5: disabling regulator
> > [   47.298071] Freezing user space processes ... (elapsed 0.008
> > seconds) done.
> > [   47.313432] OOM killer disabled.
> > [   47.316670] Freezing remaining freezable tasks ... (elapsed
> > 2.221
> > seconds) done.
> > [   49.672052] imx8m-blk-ctrl 38320000.blk-ctrl:
> > imx8m_blk_ctrl_suspend
> > start
> > [   49.704417] imx-pgc imx-pgc-domain.0: disabling regulator
> > [   49.711114] imx-pgc imx-pgc-domain.6: disabling regulator
> > [   49.819064] buck4: failed to disable: -ETIMEDOUT
> > 
> > The stack looks pretty much the same for all of them, from
> > pm_suspend()
> > over genpd_suspend_noiry().
> 
> So the GPU domain is already suspended before the system suspend,
> probably due to short runtime PM timeouts.
> 
> Can you please check at which point the i2c subsystem is suspended? I
> think we are already past that point when running the PM domain
> suspend
> from a _noirq callback. I'll take a look on how we can properly
> change
> this ordering.

hi Lucas, when I just add the same system suspend hook you added to
gpcv2 (pm_runtime_get()), I get the same timeout:

[  366.100154] Freezing remaining freezable tasks ... (elapsed 2.863
seconds) done.
[  369.228387] imx-i2c 30a50000.i2c: pm_runtime get.
[  369.234204] imx-i2c 30a40000.i2c: pm_runtime get.
[  369.239834] imx-i2c 30a30000.i2c: pm_runtime get.
[  369.247417] imx-i2c 30a20000.i2c: pm_runtime get.
[  369.277838] imx-pgc imx-pgc-domain.0: disable regulator now
[  369.284758] imx-pgc imx-pgc-domain.6: disable regulator now
[  369.394954] buck4: failed to disable: -ETIMEDOUT

do you have an idea?

                              martin



^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-04-26 10:43         ` Lucas Stach
  2022-04-26 12:12           ` Martin Kepplinger
  2022-04-29  9:52           ` Martin Kepplinger
@ 2022-05-23 12:00           ` Martin Kepplinger
  2022-07-11  9:53           ` Martin Kepplinger
  3 siblings, 0 replies; 44+ messages in thread
From: Martin Kepplinger @ 2022-05-23 12:00 UTC (permalink / raw)
  To: Lucas Stach, Adam Ford, linux-media
  Cc: aford, cphealy, kernel test robot, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

Am Dienstag, dem 26.04.2022 um 12:43 +0200 schrieb Lucas Stach:
> Am Dienstag, dem 26.04.2022 um 09:38 +0200 schrieb Martin Kepplinger:
> > Am Montag, dem 25.04.2022 um 17:34 +0200 schrieb Lucas Stach:
> > > Hi Martin,
> > > 
> > > Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin
> > > Kepplinger:
> > > > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > > > With the Hantro G1 and G2 now setup to run independently,
> > > > > update
> > > > > the device tree to allow both to operate.  This requires the
> > > > > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > > > > certain clock enabled to handle the gating of the G1 and G2
> > > > > fuses, the clock-parents and clock-rates for the various
> > > > > VPU's
> > > > > to be moved into the pgc_vpu because they cannot get re-
> > > > > parented
> > > > > once enabled, and the pgc_vpu is the highest in the chain.
> > > > > 
> > > > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > > > Reported-by: kernel test robot <lkp@intel.com>
> > > > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > index 2df2510d0118..549b2440f55d 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > > > >                                         pgc_vpu: power-
> > > > > domain@6 {
> > > > >                                                 #power-
> > > > > domain-
> > > > > cells =
> > > > > <0>;
> > > > >                                                 reg =
> > > > > <IMX8M_POWER_DOMAIN_VPU>;
> > > > > -                                               clocks =
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > +                                               clocks =
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > > > +                                                       
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > +                                                       
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                                               assigned-
> > > > > clocks =
> > > > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > > > +                                               assigned-
> > > > > clock-
> > > > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_VPU_PLL>;
> > > > > +                                               assigned-
> > > > > clock-
> > > > > rates
> > > > > = <600000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <600000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <800000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <0>;
> > > > >                                         };
> > > > >  
> > > > >                                         pgc_disp:
> > > > > power-domain@7
> > > > > {
> > > > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > > > >                         status = "disabled";
> > > > >                 };
> > > > >  
> > > > > -               vpu: video-codec@38300000 {
> > > > > -                       compatible = "nxp,imx8mq-vpu";
> > > > > -                       reg = <0x38300000 0x10000>,
> > > > > -                             <0x38310000 0x10000>,
> > > > > -                             <0x38320000 0x10000>;
> > > > > -                       reg-names = "g1", "g2", "ctrl";
> > > > > -                       interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > -                                    <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > -                       interrupt-names = "g1", "g2";
> > > > > +               vpu_g1: video-codec@38300000 {
> > > > > +                       compatible = "nxp,imx8mq-vpu-g1";
> > > > > +                       reg = <0x38300000 0x10000>;
> > > > > +                       interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>;
> > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G1>;
> > > > > +               };
> > > > > +
> > > > > +               vpu_g2: video-codec@38310000 {
> > > > > +                       compatible = "nxp,imx8mq-vpu-g2";
> > > > > +                       reg = <0x38310000 0x10000>;
> > > > > +                       interrupts = <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G2>;
> > > > > +               };
> > > > > +
> > > > > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > > > > +                       compatible = "fsl,imx8mq-vpu-blk-
> > > > > ctrl";
> > > > > +                       reg = <0x38320000 0x100>;
> > > > > +                       power-domains = <&pgc_vpu>,
> > > > > <&pgc_vpu>,
> > > > > <&pgc_vpu>;
> > > > > +                       power-domain-names = "bus", "g1",
> > > > > "g2";
> > > > >                         clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > -                                <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>,
> > > > > -                                <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > -                       clock-names = "g1", "g2", "bus";
> > > > > -                       assigned-clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_CLK_VPU_G2>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_CLK_VPU_BUS>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_VPU_PLL_BYPASS>;
> > > > > -                       assigned-clock-parents = <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_SYS1_PLL_800M>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_VPU_PLL>;
> > > > > -                       assigned-clock-rates = <600000000>,
> > > > > <600000000>,
> > > > > -                                              <800000000>,
> > > > > <0>;
> > > > > -                       power-domains = <&pgc_vpu>;
> > > > > +                                <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                       clock-names = "g1", "g2";
> > > > > +                       #power-domain-cells = <1>;
> > > > >                 };
> > > > >  
> > > > >                 pcie0: pcie@33800000 {
> > > > 
> > > > With this update, when testing suspend to ram on imx8mq, I get:
> > > > 
> > > > buck4: failed to disable: -ETIMEDOUT
> > > > 
> > > > where buck4 is power-supply of pgc_vpu. And thus the transition
> > > > to
> > > > suspend (and resuming) fails.
> > > > 
> > > > Have you tested system suspend after the imx8m-blk-ctrl update
> > > > on
> > > > imx8mq?
> > > 
> > > I haven't tested system suspend, don't know if anyone else did.
> > > However
> > > I guess that this is just uncovering a preexisting issue in the
> > > system
> > > suspend sequencing, which you would also hit if the video
> > > decoders
> > > were
> > > active at system suspend time.
> > > 
> > > My guess is that the regulator disable fails, due to the power
> > > domains
> > > being disabled quite late in the suspend sequence, where i2c
> > > communication with the PMIC is no longer possible due to i2c
> > > being
> > > suspended already or something like that. Maybe you can dig in a
> > > bit
> > > on
> > > the actual sequence on your system and we can see how we can
> > > rework
> > > things to suspend the power domains at a time where communication
> > > with
> > > the PMIC is still possible?
> > 
> > What exactly would you like to see? Here's all gpcv2 regulators
> > disabling on suspend. (gpu (domain 5) is disabled by runtime pm
> > often):
> > 
> > [   47.138700] imx-pgc imx-pgc-domain.5: disabling regulator
> > [   47.298071] Freezing user space processes ... (elapsed 0.008
> > seconds) done.
> > [   47.313432] OOM killer disabled.
> > [   47.316670] Freezing remaining freezable tasks ... (elapsed
> > 2.221
> > seconds) done.
> > [   49.672052] imx8m-blk-ctrl 38320000.blk-ctrl:
> > imx8m_blk_ctrl_suspend
> > start
> > [   49.704417] imx-pgc imx-pgc-domain.0: disabling regulator
> > [   49.711114] imx-pgc imx-pgc-domain.6: disabling regulator
> > [   49.819064] buck4: failed to disable: -ETIMEDOUT
> > 
> > The stack looks pretty much the same for all of them, from
> > pm_suspend()
> > over genpd_suspend_noiry().
> 
> So the GPU domain is already suspended before the system suspend,
> probably due to short runtime PM timeouts.
> 
> Can you please check at which point the i2c subsystem is suspended? I
> think we are already past that point when running the PM domain
> suspend
> from a _noirq callback. I'll take a look on how we can properly
> change
> this ordering.
> 
> Regards,
> Lucas
> 

hi Lucas, just to update a bit: (I rmmod hantro_vpu because it adds
another bug but let's ignore for now) when I use a mainline kernel and
for testing just ignore ETIMEDOUT in gpcv2 on regulator_disable():

-                               return ret;
+                               if (ret == -ETIMEDOUT)
+                                       ret = 0;
+                               else
+                                       return ret;

I see the error message the first time I suspend. Not the consecutive
times (and the systems seems to be working after resuming).

Now what's weird is when I suspend and resume often, after some time,
resume will definitely fail. Not sure yet where, but when I add debug
output for the kernel/ directory, that's usually about where it hangs:

[  969.620825] OOM killer enabled.
[  969.623971] Restarting tasks ... 
[  969.624230] systemd-udevd left refrigerator
[  969.624535] khugepaged left refrigerator
[  969.624568] gdbus left refrigerator
[  969.624795] alsa-sink-308b0 left refrigerator
[  969.626864] pipewire left refrigerator
[  969.626880] alsa-source-308 left refrigerator
[  969.626913] alsa-source-300 left refrigerator
[  969.626920] gmain left refrigerator
[  969.626949] gvfs-afc-volume left refrigerator
[  969.626949] systemd left refrigerator
[  969.626977] gmain left refrigerator
[  969.627009] chatty left refrigerator
[  969.627036] gmain left refrigerator
[  969.627060] gmain left refrigerator
[  969.627087] gmain left refrigerator

And the above hang ("sometimes") happens for "platform" in pm_test
already, so I guess it's purely a linux bug.

just so you know, in case that tells you anything more...

thanks,

                         martin



^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-04-26 10:43         ` Lucas Stach
                             ` (2 preceding siblings ...)
  2022-05-23 12:00           ` Martin Kepplinger
@ 2022-07-11  9:53           ` Martin Kepplinger
  2022-07-11 12:32             ` Ezequiel Garcia
  3 siblings, 1 reply; 44+ messages in thread
From: Martin Kepplinger @ 2022-07-11  9:53 UTC (permalink / raw)
  To: Lucas Stach, Adam Ford, linux-media
  Cc: aford, cphealy, kernel test robot, Ezequiel Garcia,
	Philipp Zabel, Mauro Carvalho Chehab, Rob Herring, Shawn Guo,
	Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
	NXP Linux Team, Greg Kroah-Hartman, linux-rockchip, devicetree,
	linux-arm-kernel, linux-kernel, linux-staging

Am Dienstag, dem 26.04.2022 um 12:43 +0200 schrieb Lucas Stach:
> Am Dienstag, dem 26.04.2022 um 09:38 +0200 schrieb Martin Kepplinger:
> > Am Montag, dem 25.04.2022 um 17:34 +0200 schrieb Lucas Stach:
> > > Hi Martin,
> > > 
> > > Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin
> > > Kepplinger:
> > > > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > > > With the Hantro G1 and G2 now setup to run independently,
> > > > > update
> > > > > the device tree to allow both to operate.  This requires the
> > > > > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > > > > certain clock enabled to handle the gating of the G1 and G2
> > > > > fuses, the clock-parents and clock-rates for the various
> > > > > VPU's
> > > > > to be moved into the pgc_vpu because they cannot get re-
> > > > > parented
> > > > > once enabled, and the pgc_vpu is the highest in the chain.
> > > > > 
> > > > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > > > Reported-by: kernel test robot <lkp@intel.com>
> > > > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > index 2df2510d0118..549b2440f55d 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > > > >                                         pgc_vpu: power-
> > > > > domain@6 {
> > > > >                                                 #power-
> > > > > domain-
> > > > > cells =
> > > > > <0>;
> > > > >                                                 reg =
> > > > > <IMX8M_POWER_DOMAIN_VPU>;
> > > > > -                                               clocks =
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > +                                               clocks =
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > > > +                                                       
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > +                                                       
> > > > > <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                                               assigned-
> > > > > clocks =
> > > > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > > > +                                                            
> > > > >     
> > > > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > > > +                                               assigned-
> > > > > clock-
> > > > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >     <&clk IMX8MQ_VPU_PLL>;
> > > > > +                                               assigned-
> > > > > clock-
> > > > > rates
> > > > > = <600000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <600000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <800000000>,
> > > > > +                                                            
> > > > >     
> > > > >     
> > > > >   <0>;
> > > > >                                         };
> > > > >  
> > > > >                                         pgc_disp:
> > > > > power-domain@7
> > > > > {
> > > > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > > > >                         status = "disabled";
> > > > >                 };
> > > > >  
> > > > > -               vpu: video-codec@38300000 {
> > > > > -                       compatible = "nxp,imx8mq-vpu";
> > > > > -                       reg = <0x38300000 0x10000>,
> > > > > -                             <0x38310000 0x10000>,
> > > > > -                             <0x38320000 0x10000>;
> > > > > -                       reg-names = "g1", "g2", "ctrl";
> > > > > -                       interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > -                                    <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > -                       interrupt-names = "g1", "g2";
> > > > > +               vpu_g1: video-codec@38300000 {
> > > > > +                       compatible = "nxp,imx8mq-vpu-g1";
> > > > > +                       reg = <0x38300000 0x10000>;
> > > > > +                       interrupts = <GIC_SPI 7
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>;
> > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G1>;
> > > > > +               };
> > > > > +
> > > > > +               vpu_g2: video-codec@38310000 {
> > > > > +                       compatible = "nxp,imx8mq-vpu-g2";
> > > > > +                       reg = <0x38310000 0x10000>;
> > > > > +                       interrupts = <GIC_SPI 8
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > IMX8MQ_VPUBLK_PD_G2>;
> > > > > +               };
> > > > > +
> > > > > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > > > > +                       compatible = "fsl,imx8mq-vpu-blk-
> > > > > ctrl";
> > > > > +                       reg = <0x38320000 0x100>;
> > > > > +                       power-domains = <&pgc_vpu>,
> > > > > <&pgc_vpu>,
> > > > > <&pgc_vpu>;
> > > > > +                       power-domain-names = "bus", "g1",
> > > > > "g2";
> > > > >                         clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > -                                <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>,
> > > > > -                                <&clk
> > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > -                       clock-names = "g1", "g2", "bus";
> > > > > -                       assigned-clocks = <&clk
> > > > > IMX8MQ_CLK_VPU_G1>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_CLK_VPU_G2>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_CLK_VPU_BUS>,
> > > > > -                                         <&clk
> > > > > IMX8MQ_VPU_PLL_BYPASS>;
> > > > > -                       assigned-clock-parents = <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_SYS1_PLL_800M>,
> > > > > -                                                <&clk
> > > > > IMX8MQ_VPU_PLL>;
> > > > > -                       assigned-clock-rates = <600000000>,
> > > > > <600000000>,
> > > > > -                                              <800000000>,
> > > > > <0>;
> > > > > -                       power-domains = <&pgc_vpu>;
> > > > > +                                <&clk
> > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > +                       clock-names = "g1", "g2";
> > > > > +                       #power-domain-cells = <1>;
> > > > >                 };
> > > > >  
> > > > >                 pcie0: pcie@33800000 {
> > > > 
> > > > With this update, when testing suspend to ram on imx8mq, I get:
> > > > 
> > > > buck4: failed to disable: -ETIMEDOUT
> > > > 
> > > > where buck4 is power-supply of pgc_vpu. And thus the transition
> > > > to
> > > > suspend (and resuming) fails.
> > > > 
> > > > Have you tested system suspend after the imx8m-blk-ctrl update
> > > > on
> > > > imx8mq?
> > > 
> > > I haven't tested system suspend, don't know if anyone else did.
> > > However
> > > I guess that this is just uncovering a preexisting issue in the
> > > system
> > > suspend sequencing, which you would also hit if the video
> > > decoders
> > > were
> > > active at system suspend time.
> > > 
> > > My guess is that the regulator disable fails, due to the power
> > > domains
> > > being disabled quite late in the suspend sequence, where i2c
> > > communication with the PMIC is no longer possible due to i2c
> > > being
> > > suspended already or something like that. Maybe you can dig in a
> > > bit
> > > on
> > > the actual sequence on your system and we can see how we can
> > > rework
> > > things to suspend the power domains at a time where communication
> > > with
> > > the PMIC is still possible?
> > 
> > What exactly would you like to see? Here's all gpcv2 regulators
> > disabling on suspend. (gpu (domain 5) is disabled by runtime pm
> > often):
> > 
> > [   47.138700] imx-pgc imx-pgc-domain.5: disabling regulator
> > [   47.298071] Freezing user space processes ... (elapsed 0.008
> > seconds) done.
> > [   47.313432] OOM killer disabled.
> > [   47.316670] Freezing remaining freezable tasks ... (elapsed
> > 2.221
> > seconds) done.
> > [   49.672052] imx8m-blk-ctrl 38320000.blk-ctrl:
> > imx8m_blk_ctrl_suspend
> > start
> > [   49.704417] imx-pgc imx-pgc-domain.0: disabling regulator
> > [   49.711114] imx-pgc imx-pgc-domain.6: disabling regulator
> > [   49.819064] buck4: failed to disable: -ETIMEDOUT
> > 
> > The stack looks pretty much the same for all of them, from
> > pm_suspend()
> > over genpd_suspend_noiry().
> 
> So the GPU domain is already suspended before the system suspend,
> probably due to short runtime PM timeouts.
> 
> Can you please check at which point the i2c subsystem is suspended? I
> think we are already past that point when running the PM domain
> suspend
> from a _noirq callback. I'll take a look on how we can properly
> change
> this ordering.
> 
> Regards,
> Lucas
> 

hi Lucas, sorry for not following up on this for so long. This fixes
suspend/resume for me:

https://lore.kernel.org/linux-arm-kernel/20220711094549.3445566-1-martin.kepplinger@puri.sm/T/#t

thank you for you help so far,

                             martin


^ permalink raw reply	[flat|nested] 44+ messages in thread

* Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
  2022-07-11  9:53           ` Martin Kepplinger
@ 2022-07-11 12:32             ` Ezequiel Garcia
  0 siblings, 0 replies; 44+ messages in thread
From: Ezequiel Garcia @ 2022-07-11 12:32 UTC (permalink / raw)
  To: Martin Kepplinger
  Cc: Lucas Stach, Adam Ford, linux-media, Adam Ford-BE, Chris Healy,
	kernel test robot, Philipp Zabel, Mauro Carvalho Chehab,
	Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
	Fabio Estevam, NXP Linux Team, Greg Kroah-Hartman,
	open list:ARM/Rockchip SoC...,
	devicetree, linux-arm-kernel, Linux Kernel Mailing List,
	open list:STAGING SUBSYSTEM

Hi Martin,

On Mon, Jul 11, 2022 at 6:53 AM Martin Kepplinger
<martin.kepplinger@puri.sm> wrote:
>
> Am Dienstag, dem 26.04.2022 um 12:43 +0200 schrieb Lucas Stach:
> > Am Dienstag, dem 26.04.2022 um 09:38 +0200 schrieb Martin Kepplinger:
> > > Am Montag, dem 25.04.2022 um 17:34 +0200 schrieb Lucas Stach:
> > > > Hi Martin,
> > > >
> > > > Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin
> > > > Kepplinger:
> > > > > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > > > > With the Hantro G1 and G2 now setup to run independently,
> > > > > > update
> > > > > > the device tree to allow both to operate.  This requires the
> > > > > > vpu-blk-ctrl node to be configured.  Since vpu-blk-ctrl needs
> > > > > > certain clock enabled to handle the gating of the G1 and G2
> > > > > > fuses, the clock-parents and clock-rates for the various
> > > > > > VPU's
> > > > > > to be moved into the pgc_vpu because they cannot get re-
> > > > > > parented
> > > > > > once enabled, and the pgc_vpu is the highest in the chain.
> > > > > >
> > > > > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > > > > Reported-by: kernel test robot <lkp@intel.com>
> > > > > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > > > > >
> > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > > index 2df2510d0118..549b2440f55d 100644
> > > > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > > > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > > > > >                                         pgc_vpu: power-
> > > > > > domain@6 {
> > > > > >                                                 #power-
> > > > > > domain-
> > > > > > cells =
> > > > > > <0>;
> > > > > >                                                 reg =
> > > > > > <IMX8M_POWER_DOMAIN_VPU>;
> > > > > > -                                               clocks =
> > > > > > <&clk
> > > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > > +                                               clocks =
> > > > > > <&clk
> > > > > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > > > > +
> > > > > > <&clk
> > > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > > +
> > > > > > <&clk
> > > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > > +                                               assigned-
> > > > > > clocks =
> > > > > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > > > > +
> > > > > >
> > > > > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > > > > +
> > > > > >
> > > > > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > > > > +
> > > > > >
> > > > > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > > > > +                                               assigned-
> > > > > > clock-
> > > > > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > > +
> > > > > >
> > > > > >
> > > > > >     <&clk IMX8MQ_VPU_PLL_OUT>,
> > > > > > +
> > > > > >
> > > > > >
> > > > > >     <&clk IMX8MQ_SYS1_PLL_800M>,
> > > > > > +
> > > > > >
> > > > > >
> > > > > >     <&clk IMX8MQ_VPU_PLL>;
> > > > > > +                                               assigned-
> > > > > > clock-
> > > > > > rates
> > > > > > = <600000000>,
> > > > > > +
> > > > > >
> > > > > >
> > > > > >   <600000000>,
> > > > > > +
> > > > > >
> > > > > >
> > > > > >   <800000000>,
> > > > > > +
> > > > > >
> > > > > >
> > > > > >   <0>;
> > > > > >                                         };
> > > > > >
> > > > > >                                         pgc_disp:
> > > > > > power-domain@7
> > > > > > {
> > > > > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > > > > >                         status = "disabled";
> > > > > >                 };
> > > > > >
> > > > > > -               vpu: video-codec@38300000 {
> > > > > > -                       compatible = "nxp,imx8mq-vpu";
> > > > > > -                       reg = <0x38300000 0x10000>,
> > > > > > -                             <0x38310000 0x10000>,
> > > > > > -                             <0x38320000 0x10000>;
> > > > > > -                       reg-names = "g1", "g2", "ctrl";
> > > > > > -                       interrupts = <GIC_SPI 7
> > > > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > > > -                                    <GIC_SPI 8
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > -                       interrupt-names = "g1", "g2";
> > > > > > +               vpu_g1: video-codec@38300000 {
> > > > > > +                       compatible = "nxp,imx8mq-vpu-g1";
> > > > > > +                       reg = <0x38300000 0x10000>;
> > > > > > +                       interrupts = <GIC_SPI 7
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > +                       clocks = <&clk
> > > > > > IMX8MQ_CLK_VPU_G1_ROOT>;
> > > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > > IMX8MQ_VPUBLK_PD_G1>;
> > > > > > +               };
> > > > > > +
> > > > > > +               vpu_g2: video-codec@38310000 {
> > > > > > +                       compatible = "nxp,imx8mq-vpu-g2";
> > > > > > +                       reg = <0x38310000 0x10000>;
> > > > > > +                       interrupts = <GIC_SPI 8
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > +                       clocks = <&clk
> > > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > > +                       power-domains = <&vpu_blk_ctrl
> > > > > > IMX8MQ_VPUBLK_PD_G2>;
> > > > > > +               };
> > > > > > +
> > > > > > +               vpu_blk_ctrl: blk-ctrl@38320000 {
> > > > > > +                       compatible = "fsl,imx8mq-vpu-blk-
> > > > > > ctrl";
> > > > > > +                       reg = <0x38320000 0x100>;
> > > > > > +                       power-domains = <&pgc_vpu>,
> > > > > > <&pgc_vpu>,
> > > > > > <&pgc_vpu>;
> > > > > > +                       power-domain-names = "bus", "g1",
> > > > > > "g2";
> > > > > >                         clocks = <&clk
> > > > > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > > > > -                                <&clk
> > > > > > IMX8MQ_CLK_VPU_G2_ROOT>,
> > > > > > -                                <&clk
> > > > > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > > > > -                       clock-names = "g1", "g2", "bus";
> > > > > > -                       assigned-clocks = <&clk
> > > > > > IMX8MQ_CLK_VPU_G1>,
> > > > > > -                                         <&clk
> > > > > > IMX8MQ_CLK_VPU_G2>,
> > > > > > -                                         <&clk
> > > > > > IMX8MQ_CLK_VPU_BUS>,
> > > > > > -                                         <&clk
> > > > > > IMX8MQ_VPU_PLL_BYPASS>;
> > > > > > -                       assigned-clock-parents = <&clk
> > > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > > -                                                <&clk
> > > > > > IMX8MQ_VPU_PLL_OUT>,
> > > > > > -                                                <&clk
> > > > > > IMX8MQ_SYS1_PLL_800M>,
> > > > > > -                                                <&clk
> > > > > > IMX8MQ_VPU_PLL>;
> > > > > > -                       assigned-clock-rates = <600000000>,
> > > > > > <600000000>,
> > > > > > -                                              <800000000>,
> > > > > > <0>;
> > > > > > -                       power-domains = <&pgc_vpu>;
> > > > > > +                                <&clk
> > > > > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > > > > +                       clock-names = "g1", "g2";
> > > > > > +                       #power-domain-cells = <1>;
> > > > > >                 };
> > > > > >
> > > > > >                 pcie0: pcie@33800000 {
> > > > >
> > > > > With this update, when testing suspend to ram on imx8mq, I get:
> > > > >
> > > > > buck4: failed to disable: -ETIMEDOUT
> > > > >
> > > > > where buck4 is power-supply of pgc_vpu. And thus the transition
> > > > > to
> > > > > suspend (and resuming) fails.
> > > > >
> > > > > Have you tested system suspend after the imx8m-blk-ctrl update
> > > > > on
> > > > > imx8mq?
> > > >
> > > > I haven't tested system suspend, don't know if anyone else did.
> > > > However
> > > > I guess that this is just uncovering a preexisting issue in the
> > > > system
> > > > suspend sequencing, which you would also hit if the video
> > > > decoders
> > > > were
> > > > active at system suspend time.
> > > >
> > > > My guess is that the regulator disable fails, due to the power
> > > > domains
> > > > being disabled quite late in the suspend sequence, where i2c
> > > > communication with the PMIC is no longer possible due to i2c
> > > > being
> > > > suspended already or something like that. Maybe you can dig in a
> > > > bit
> > > > on
> > > > the actual sequence on your system and we can see how we can
> > > > rework
> > > > things to suspend the power domains at a time where communication
> > > > with
> > > > the PMIC is still possible?
> > >
> > > What exactly would you like to see? Here's all gpcv2 regulators
> > > disabling on suspend. (gpu (domain 5) is disabled by runtime pm
> > > often):
> > >
> > > [   47.138700] imx-pgc imx-pgc-domain.5: disabling regulator
> > > [   47.298071] Freezing user space processes ... (elapsed 0.008
> > > seconds) done.
> > > [   47.313432] OOM killer disabled.
> > > [   47.316670] Freezing remaining freezable tasks ... (elapsed
> > > 2.221
> > > seconds) done.
> > > [   49.672052] imx8m-blk-ctrl 38320000.blk-ctrl:
> > > imx8m_blk_ctrl_suspend
> > > start
> > > [   49.704417] imx-pgc imx-pgc-domain.0: disabling regulator
> > > [   49.711114] imx-pgc imx-pgc-domain.6: disabling regulator
> > > [   49.819064] buck4: failed to disable: -ETIMEDOUT
> > >
> > > The stack looks pretty much the same for all of them, from
> > > pm_suspend()
> > > over genpd_suspend_noiry().
> >
> > So the GPU domain is already suspended before the system suspend,
> > probably due to short runtime PM timeouts.
> >
> > Can you please check at which point the i2c subsystem is suspended? I
> > think we are already past that point when running the PM domain
> > suspend
> > from a _noirq callback. I'll take a look on how we can properly
> > change
> > this ordering.
> >
> > Regards,
> > Lucas
> >
>
> hi Lucas, sorry for not following up on this for so long. This fixes
> suspend/resume for me:
>
> https://lore.kernel.org/linux-arm-kernel/20220711094549.3445566-1-martin.kepplinger@puri.sm/T/#t
>
> thank you for you help so far,
>

Thanks a lot for keeping us posted. The fix for suspend/resume
looks great!

Ezequiel

^ permalink raw reply	[flat|nested] 44+ messages in thread

end of thread, other threads:[~2022-07-11 12:32 UTC | newest]

Thread overview: 44+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
2022-01-25 17:11 ` [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference Adam Ford
2022-01-25 18:22   ` Lucas Stach
2022-01-25 18:57   ` Ezequiel Garcia
2022-01-26  6:42   ` (EXT) " Alexander Stein
2022-02-09  7:10   ` Shawn Guo
2022-01-25 17:11 ` [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains Adam Ford
2022-01-27  8:46   ` Hans Verkuil
2022-02-03 13:16     ` Adam Ford
2022-02-05 14:01     ` Ezequiel Garcia
2022-02-09  7:14   ` Shawn Guo
2022-01-25 17:11 ` [PATCH V4 03/11] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl Adam Ford
2022-02-09  7:16   ` Shawn Guo
2022-01-25 17:11 ` [PATCH V4 04/11] soc: imx: imx8m-blk-ctrl: add " Adam Ford
2022-02-09  7:19   ` Shawn Guo
2022-01-25 17:11 ` [PATCH V4 05/11] dt-bindings: media: nxp, imx8mq-vpu: Split G1 and G2 nodes Adam Ford
2022-01-25 17:11 ` [PATCH V4 06/11] media: hantro: Allow i.MX8MQ G1 and G2 to run independently Adam Ford
2022-01-25 17:11 ` [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Adam Ford
2022-01-25 18:20   ` Lucas Stach
2022-01-25 19:04   ` Ezequiel Garcia
2022-01-25 19:08     ` Adam Ford
2022-02-09  7:27     ` Shawn Guo
2022-04-25 15:22   ` Martin Kepplinger
2022-04-25 15:34     ` Lucas Stach
2022-04-25 15:47       ` Adam Ford
2022-04-26 10:28         ` Martin Kepplinger
2022-04-26 10:40           ` Lucas Stach
2022-04-26  7:38       ` Martin Kepplinger
2022-04-26 10:43         ` Lucas Stach
2022-04-26 12:12           ` Martin Kepplinger
2022-04-29  9:52           ` Martin Kepplinger
2022-05-23 12:00           ` Martin Kepplinger
2022-07-11  9:53           ` Martin Kepplinger
2022-07-11 12:32             ` Ezequiel Garcia
2022-01-25 17:11 ` [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging Adam Ford
2022-01-25 18:19   ` Lucas Stach
2022-02-09  7:33   ` Shawn Guo
2022-01-25 17:11 ` [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm Adam Ford
2022-01-26  6:45   ` (EXT) " Alexander Stein
2022-02-04 23:16   ` Rob Herring
2022-01-25 17:11 ` [PATCH V4 10/11] media: hantro: Add support for i.MX8MM Hantro-G1 Adam Ford
2022-01-25 17:11 ` [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders Adam Ford
2022-01-25 18:21   ` Lucas Stach
2022-02-09  7:35   ` Shawn Guo

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