From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61092C433E1 for ; Tue, 2 Jun 2020 12:06:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 40FC9207ED for ; Tue, 2 Jun 2020 12:06:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726606AbgFBMGS (ORCPT ); Tue, 2 Jun 2020 08:06:18 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:5333 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725921AbgFBMGR (ORCPT ); Tue, 2 Jun 2020 08:06:17 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 81E03B2E8FAAB54CD06E; Tue, 2 Jun 2020 20:06:15 +0800 (CST) Received: from [127.0.0.1] (10.173.220.25) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Tue, 2 Jun 2020 20:06:09 +0800 Subject: Re: [RFC PATCH v4 2/2] arm64: tlb: Use the TLBI RANGE feature in arm64 To: , , , , , , CC: , , , , , , , , References: <20200601144713.2222-1-yezhenyu2@huawei.com> <20200601144713.2222-3-yezhenyu2@huawei.com> From: Zhenyu Ye Message-ID: <7f15f835-cf73-be5b-8bb0-cabb6e4eeed2@huawei.com> Date: Tue, 2 Jun 2020 20:06:08 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <20200601144713.2222-3-yezhenyu2@huawei.com> Content-Type: text/plain; charset="gbk" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.220.25] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, Some optimizations to the codes: On 2020/6/1 22:47, Zhenyu Ye wrote: > - start = __TLBI_VADDR(start, asid); > - end = __TLBI_VADDR(end, asid); > + /* > + * The minimum size of TLB RANGE is 2 pages; > + * Use normal TLB instruction to handle odd pages. > + * If the stride != PAGE_SIZE, this will never happen. > + */ > + if (range_pages % 2 == 1) { > + addr = __TLBI_VADDR(start, asid); > + __tlbi_last_level(vale1is, vae1is, addr, last_level); > + start += 1 << PAGE_SHIFT; > + range_pages >>= 1; > + } > We flush a single page here, and below loop does the same thing if cpu not support TLB RANGE feature. So may we use a goto statement to simplify the code. > + while (range_pages > 0) { > + if (cpus_have_const_cap(ARM64_HAS_TLBI_RANGE) && > + stride == PAGE_SIZE) { > + num = (range_pages & TLB_RANGE_MASK) - 1; > + if (num >= 0) { > + addr = __TLBI_VADDR_RANGE(start, asid, scale, > + num, 0); > + __tlbi_last_level(rvale1is, rvae1is, addr, > + last_level); > + start += __TLBI_RANGE_SIZES(num, scale); > + } > + scale++; > + range_pages >>= TLB_RANGE_MASK_SHIFT; > + continue; > } > + > + addr = __TLBI_VADDR(start, asid); > + __tlbi_last_level(vale1is, vae1is, addr, last_level); > + start += stride; > + range_pages -= stride >> 12; > } > dsb(ish); > } > Just like: --8<--- if (range_pages %2 == 1) goto flush_single_tlb; while (range_pages > 0) { if (cpus_have_const_cap(ARM64_HAS_TLBI_RANGE) && stride == PAGE_SIZE) { num = ((range_pages >> 1) & TLB_RANGE_MASK) - 1; if (num >= 0) { addr = __TLBI_VADDR_RANGE(start, asid, scale, num, 0); __tlbi_last_level(rvale1is, rvae1is, addr, last_level); start += __TLBI_RANGE_SIZES(num, scale); } scale++; range_pages >>= TLB_RANGE_MASK_SHIFT; continue; } flush_single_tlb: addr = __TLBI_VADDR(start, asid); __tlbi_last_level(vale1is, vae1is, addr, last_level); start += stride; range_pages -= stride >> PAGE_SHIFT; } --8<---