From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Hal Feng <hal.feng@starfivetech.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org
Cc: Conor Dooley <conor@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Linus Walleij <linus.walleij@linaro.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Jianlong Huang <jianlong.huang@starfivetech.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/5] dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
Date: Mon, 21 Nov 2022 09:44:00 +0100 [thread overview]
Message-ID: <7f78e57a-d9be-b1e9-d161-40b1f66e3804@linaro.org> (raw)
In-Reply-To: <20221118011108.70715-4-hal.feng@starfivetech.com>
On 18/11/2022 02:11, Hal Feng wrote:
> From: Jianlong Huang <jianlong.huang@starfivetech.com>
>
> Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller.
>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../pinctrl/starfive,jh7110-aon-pinctrl.yaml | 134 ++++++++++++++++++
> 1 file changed, 134 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
> new file mode 100644
> index 000000000000..1dd000e1f614
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
> @@ -0,0 +1,134 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Aon Pin Controller
> +
> +description: |
> + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
> +
> + Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO4
> + can be multiplexed and have configurable bias, drive strength,
> + schmitt trigger etc.
> + Some peripherals have their I/O go through the 4 "GPIOs". This also
> + includes PWM.
> +
> +maintainers:
> + - Jianlong Huang <jianlong.huang@starfivetech.com>
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-aon-pinctrl
> +
> + reg:
> + maxItems: 1
> +
> + reg-names:
> + items:
> + - const: control
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + gpio-controller: true
> +
> + "#gpio-cells":
> + const: 2
> +
> + interrupts:
> + maxItems: 1
> + description: The GPIO parent interrupt.
Same comments apply plus one more.
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 2
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - gpio-controller
> + - "#gpio-cells"
> + - interrupts
> + - interrupt-controller
> + - "#interrupt-cells"
"required:" goes after patternProperties.
> +
> +patternProperties:
> + '-[0-9]+$':
Same comment.
> + type: object
> + patternProperties:
> + '-pins$':
> + type: object
> + description: |
> + A pinctrl node should contain at least one subnode representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to
> + muxer configuration, system signal configuration, pin groups for
> + vin/vout module, pin voltage, mux functions for output, mux functions
> + for output enable, mux functions for input.
> +
> + properties:
> + pinmux:
> + description: |
> + The list of GPIOs and their mux settings that properties in the
> + node apply to. This should be set using the GPIOMUX macro.
> + $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux"
> +
> + bias-disable: true
> +
> + bias-pull-up:
> + type: boolean
> +
> + bias-pull-down:
> + type: boolean
> +
> + drive-strength:
> + enum: [ 2, 4, 8, 12 ]
> +
> + input-enable: true
> +
> + input-disable: true
> +
> + input-schmitt-enable: true
> +
> + input-schmitt-disable: true
> +
> + slew-rate:
> + maximum: 1
> +
> + additionalProperties: false
> +
> + additionalProperties: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/starfive-jh7110.h>
> + #include <dt-bindings/reset/starfive-jh7110.h>
> + #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
Same comment.
> +
> + gpioa: gpio@17020000 {
> + compatible = "starfive,jh7110-aon-pinctrl";
> + reg = <0x0 0x17020000 0x0 0x10000>;
> + reg-names = "control";
> + resets = <&aoncrg_rst JH7110_AONRST_AON_IOMUX>;
> + interrupts = <85>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + };
> + };
> +
> +...
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-11-21 8:44 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-18 1:11 [PATCH v2 0/5] Basic pinctrl support for StarFive JH7110 RISC-V SoC Hal Feng
2022-11-18 1:11 ` [PATCH v2 1/5] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Hal Feng
2022-11-21 8:38 ` Krzysztof Kozlowski
2022-11-21 8:39 ` Krzysztof Kozlowski
2022-11-28 0:48 ` Jianlong Huang
2022-11-28 8:32 ` Krzysztof Kozlowski
2022-11-29 1:47 ` Jianlong Huang
2022-11-29 7:49 ` Krzysztof Kozlowski
2022-11-29 14:46 ` Jianlong Huang
2022-11-29 14:58 ` Krzysztof Kozlowski
2022-11-29 15:58 ` Jianlong Huang
2022-11-29 16:02 ` Krzysztof Kozlowski
2022-12-01 9:31 ` Jianlong Huang
2022-12-07 13:14 ` Emil Renner Berthing
2022-11-18 1:11 ` [PATCH v2 2/5] dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl Hal Feng
2022-11-18 3:56 ` Rob Herring
2022-11-18 6:56 ` Hal Feng
2022-11-21 8:43 ` Krzysztof Kozlowski
2022-11-28 1:04 ` Jianlong Huang
2022-12-07 13:18 ` Emil Renner Berthing
2022-12-09 3:13 ` Icenowy Zheng
2022-11-18 1:11 ` [PATCH v2 3/5] dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl Hal Feng
2022-11-21 8:44 ` Krzysztof Kozlowski [this message]
2022-11-28 1:15 ` Jianlong Huang
2022-12-07 13:21 ` Emil Renner Berthing
2022-11-18 1:11 ` [PATCH v2 4/5] pinctrl: starfive: Add StarFive JH7110 sys controller driver Hal Feng
2022-12-07 13:47 ` Emil Renner Berthing
2022-11-18 1:11 ` [PATCH v2 5/5] pinctrl: starfive: Add StarFive JH7110 aon " Hal Feng
2022-11-18 7:17 ` [PATCH v2 0/5] Basic pinctrl support for StarFive JH7110 RISC-V SoC Hal Feng
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