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[71.197.186.152]) by smtp.googlemail.com with ESMTPSA id 196sm4065985pfy.167.2019.06.28.11.08.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Jun 2019 11:08:23 -0700 (PDT) From: Kevin Hilman To: Neil Armstrong , jbrunet@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, martin.blumenstingl@googlemail.com, linux-gpio@vger.kernel.org, Neil Armstrong Subject: Re: [RFC/RFT v2 12/14] arm64: dts: meson-g12a: enable DVFS on G12A boards In-Reply-To: <20190626090632.7540-13-narmstrong@baylibre.com> References: <20190626090632.7540-1-narmstrong@baylibre.com> <20190626090632.7540-13-narmstrong@baylibre.com> Date: Fri, 28 Jun 2019 11:08:22 -0700 Message-ID: <7himspr3ah.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Neil Armstrong writes: > Enable DVFS for the U200, SEI520 and X96-Max Amlogic G12A based board > by setting the clock, OPP and supply for each CPU cores. > > The CPU cluster power supply can achieve 0.73V to 1.01V using a PWM > output clocked at 800KHz with an inverse duty-cycle. > > DVFS has been tested by running the arm64 cpuburn at [1] and cycling > between all the possible cpufreq translations and checking the final > frequency using the clock-measurer, script at [2]. > > [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S > [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f > > Signed-off-by: Neil Armstrong [...] > @@ -297,6 +316,34 @@ > status = "okay"; > }; > > +&cpu0 { > + cpu-supply = <&vddcpu>; > + operating-points-v2 = <&cpu_opp_table>; > + clocks = <&clkc CLKID_CPU_CLK>; > + clock-latency = <50000>; > +}; > + > +&cpu1 { > + cpu-supply = <&vddcpu>; > + operating-points-v2 = <&cpu_opp_table>; > + clocks = <&clkc CLKID_CPU_CLK>; > + clock-latency = <50000>; > +}; > + > +&cpu2 { > + cpu-supply = <&vddcpu>; > + operating-points-v2 = <&cpu_opp_table>; > + clocks = <&clkc CLKID_CPU_CLK>; > + clock-latency = <50000>; > +}; > + > +&cpu3 { > + cpu-supply = <&vddcpu>; > + operating-points-v2 = <&cpu_opp_table>; > + clocks = <&clkc CLKID_CPU_CLK>; > + clock-latency = <50000>; > +}; Just curious where this max clock transtion (clock-latency) value came from. Were you able to measure that somehow? Kevin