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Tue, 14 May 2019 17:10:49 -0700 (PDT) Received: from localhost ([2601:602:9200:a1a5:fd66:a9bc:7c2c:636a]) by smtp.googlemail.com with ESMTPSA id f17sm262534pgv.16.2019.05.14.17.10.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 17:10:48 -0700 (PDT) From: Kevin Hilman To: Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/5] arm64: dts: meson: g12a: add ethernet pinctrl definitions In-Reply-To: <7244c6d3e81e7bbb84ac508399ab64e236051673.camel@baylibre.com> References: <20190510164940.13496-1-jbrunet@baylibre.com> <20190510164940.13496-3-jbrunet@baylibre.com> <7244c6d3e81e7bbb84ac508399ab64e236051673.camel@baylibre.com> Date: Tue, 14 May 2019 17:10:47 -0700 Message-ID: <7hpnokd1bs.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Jerome Brunet writes: > On Sat, 2019-05-11 at 19:06 +0200, Martin Blumenstingl wrote: >> Hi Jerome, >> >> On Fri, May 10, 2019 at 6:49 PM Jerome Brunet wrote: >> > Add the ethernet pinctrl settings for RMII, RGMII and internal phy leds >> > >> > Signed-off-by: Jerome Brunet >> > --- >> > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 37 +++++++++++++++++++++ >> > 1 file changed, 37 insertions(+) >> > >> > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> > index a32db09809f7..fe0f73730525 100644 >> > --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> > +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> > @@ -206,6 +206,43 @@ >> > }; >> > }; >> > >> > + eth_leds_pins: eth-leds { >> > + mux { >> > + groups = "eth_link_led", >> > + "eth_act_led"; >> > + function = "eth"; >> > + bias-disable; >> > + }; >> > + }; >> > + >> > + eth_rmii_pins: eth-rmii { >> > + mux { >> > + groups = "eth_mdio", >> > + "eth_mdc", >> > + "eth_rgmii_rx_clk", >> > + "eth_rx_dv", >> > + "eth_rxd0", >> > + "eth_rxd1", >> > + "eth_txen", >> > + "eth_txd0", >> > + "eth_txd1"; >> > + function = "eth"; >> > + bias-disable; >> > + }; >> > + }; >> > + >> > + eth_rgmii_pins: eth-rgmii { >> > + mux { >> > + groups = "eth_rxd2_rgmii", >> > + "eth_rxd3_rgmii", >> > + "eth_rgmii_tx_clk", >> > + "eth_txd2_rgmii", >> > + "eth_txd3_rgmii"; >> > + function = "eth"; >> > + bias-disable; >> > + }; >> > + }; >> it seems that the group definition is incomplete (missing things like >> eth_mdc, eth_rx_dv, ...) >> >> we could also mix the eth_rmii_pins and eth_rgmii_pins in a board.dts >> (maybe that was your idea in the first place?): > > yes that's the idea > >> phy-mode = "rgmii"; >> pinctrl-0 = <ð_rmii_pins>, <ð_rgmii_pins>; >> pinctrl-names = "default"; >> however, in this case I would prefer if "eth_rmii_pins" was named only >> "eth_pins" (following mostly what Amlogic does with the pin group >> naming: eth_* for pins that are valid in both, rmii and rgmii mode and >> eth*rgmii* for pins that are only valid in rgmii mode) > > I can't say I share your preference. I let Kevin decide what he wants. > It seems we've gone the eth_pins route for meson-gxl.dtsi, so I'd prefer to be consistent with that. Kevin