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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id jr16-20020a170906a99000b006e4c05e8919sm950871ejb.35.2022.04.22.10.34.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Apr 2022 10:34:54 -0700 (PDT) Message-ID: <811bf944-a230-ab9b-583a-840e57af8a1e@linaro.org> Date: Fri, 22 Apr 2022 19:34:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH V4 01/14] dt-bindings: cpufreq: mediatek: Add MediaTek CCI property Content-Language: en-US From: Krzysztof Kozlowski To: Rex-BC Chen , rafael@kernel.org, viresh.kumar@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com Cc: jia-wei.chang@mediatek.com, roger.lu@mediatek.com, hsinyi@google.com, khilman@baylibre.com, angelogioacchino.delregno@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20220422075239.16437-1-rex-bc.chen@mediatek.com> <20220422075239.16437-2-rex-bc.chen@mediatek.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/04/2022 19:26, Krzysztof Kozlowski wrote: > On 22/04/2022 09:52, Rex-BC Chen wrote: >> MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module >> for scaling clock frequency and adjust voltage. >> The phandle could be linked between CPU and MediaTek CCI for some >> MediaTek SoCs, like MT8183 and MT8186. >> Therefore, we add this property in cpufreq-mediatek.txt. >> >> Signed-off-by: Rex-BC Chen >> --- >> .../devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt >> index b8233ec91d3d..3387e1e2a2df 100644 >> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt >> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt >> @@ -20,6 +20,11 @@ Optional properties: >> Vsram to fit SoC specific needs. When absent, the voltage scaling >> flow is handled by hardware, hence no software "voltage tracking" is >> needed. >> +- mediatek,cci: >> + MediaTek Cache Coherent Interconnect (CCI) uses the software devfreq module to >> + scale the clock frequency and adjust the voltage. > > Devfreq is a SW mechanism, it should not be part of bindings description. > >> + For details, please refer to >> + Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml > > Since the file does not exist, I have troubles reviewing it. First of > all, you already have "mediatek,cci-control" property in DT, so why > using different name? > > Second, it looks like you want to put devfreq into bindings instead of > using proper interconnect bindings. Actually judging by the driver this looks like some device-boot-time-ordering, so I wonder whether this is a proper way to express it. Best regards, Krzysztof