From: <Tudor.Ambarus@microchip.com>
To: <boris.brezillon@collabora.com>
Cc: <marek.vasut@gmail.com>, <vigneshr@ti.com>,
<miquel.raynal@bootlin.com>, <richard@nod.at>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 7/7] mtd: spi-nor: Rework the disabling of block write protection
Date: Sun, 25 Aug 2019 12:57:35 +0000 [thread overview]
Message-ID: <836fcecd-766c-c7e3-74aa-06a148b146f8@microchip.com> (raw)
In-Reply-To: <20190825142421.35d31a9b@collabora.com>
On 08/25/2019 03:24 PM, Boris Brezillon wrote:
> On Sat, 24 Aug 2019 12:00:48 +0000
> <Tudor.Ambarus@microchip.com> wrote:
>
>> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>>
>> Get rid of MFR handling and implement specific manufacturer
>> default_init() fixup hooks.
>>
>> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>> ---
>> drivers/mtd/spi-nor/spi-nor.c | 30 ++++++++++++++++++++----------
>> 1 file changed, 20 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> index fc9e14777212..f4e9fcca619f 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@ -4146,6 +4146,16 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
>> return err;
>> }
>>
>> +static void atmel_set_default_init(struct spi_nor *nor)
>> +{
>> + nor->params.disable_block_protection = spi_nor_clear_sr_bp;
>> +}
>> +
>> +static void intel_set_default_init(struct spi_nor *nor)
>> +{
>> + nor->params.disable_block_protection = spi_nor_clear_sr_bp;
>
> That's weird: you can unlock blocks but locking is not
> explicitly flagged as supported (SNOR_F_HAS_LOCK is not set). Is that
> expected?
Yes. Manufacturers have different methods for locking/unlocking blocks of
memory. Right now we support just the stm/sr locking operations. sst26vf064b for
example, uses dedicated registers for reading/writing which blocks are
protected, and not the Status Register.
The reason for having disable_block_protection(), is that some spi-nor flashes
are write protected by default after a power-on reset cycle, in order to avoid
inadvertent writes during power-up. Backward compatibility imposes to disable
the write block protection at power-up by default, so that you can erase/write
the memory without having to send an unlock-all command. Which is bad in my
opinion and that's why I proposed https://patchwork.ozlabs.org/patch/1133278/.
Even if sst26vf064b does not yet have the lock ops implemented (SNOR_F_HAS_LOCK
is not set), I would like to be able to interact with it, so to disable the
block protection at power-up. This flash, and others, support a Global Unlock
Command which unlocks the entire memory array in a single cycle. We can't
determine who supports this command purely by manufacturer type, and it's not
discoverable through SFDP, so we'll have to add a nor->info flag for it:
UNLOCK_GLOBAL_BLOCK (see https://patchwork.ozlabs.org/patch/1152606/).
In conclusion, even if SNOR_F_HAS_LOCK is not set (the locking ops are not
implemented), we can still have disable_block_protection() mechanisms to unlock
the entire flash at power-up.
>
>> +}
>> +
>> static void macronix_set_default_init(struct spi_nor *nor)
>> {
>> nor->params.quad_enable = macronix_quad_enable;
>> @@ -4173,6 +4183,14 @@ static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
>> {
>> /* Init flash parameters based on MFR */
>> switch (JEDEC_MFR(nor->info)) {
>> + case SNOR_MFR_ATMEL:
>> + atmel_set_default_init(nor);
>> + break;
>> +
>> + case SNOR_MFR_INTEL:
>> + intel_set_default_init(nor);
>> + break;
>> +
>> case SNOR_MFR_MACRONIX:
>> macronix_set_default_init(nor);
>> break;
>> @@ -4760,18 +4778,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
>> if (info->flags & SPI_S3AN)
>> nor->flags |= SNOR_F_READY_XSR_RDY;
>>
>> - if (info->flags & SPI_NOR_HAS_LOCK)
>> + if (info->flags & SPI_NOR_HAS_LOCK) {
>
> If this flag implies SR_BP-based locking we should really rename it into
> SPI_NOR_HAS_SR_BP_LOCK to avoid any confusion.
Not only SR-based locking, should be a general flag that indicates that locking
ops are supported whichever they are. I would keep the SPI_NOR_HAS_LOCK and let
the manufacturer set its locking ops using the ->default_init() hook.
>
>> nor->flags |= SNOR_F_HAS_LOCK;
>> -
>> - /*
>> - * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
>> - * with the software protection bits set.
>> - */
>> - if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
>> - JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
>> - JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
>> - nor->info->flags & SPI_NOR_HAS_LOCK)
>> nor->params.disable_block_protection = spi_nor_clear_sr_bp;
>> + }
>>
>> /* Init flash parameters based on flash_info struct and SFDP */
>> spi_nor_init_params(nor);
>
>
next prev parent reply other threads:[~2019-08-25 12:57 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-24 12:00 [PATCH v2 0/7] mtd: spi-nor: move manuf out of the core - batch 1 Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 1/7] mtd: spi-nor: Add default_init() hook to tweak flash parameters Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 2/7] mtd: spi-nor: Add a default_init() fixup hook for gd25q256 Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 3/7] mtd: spi_nor: Move manufacturer quad_enable() in ->default_init() Tudor.Ambarus
2019-08-25 11:47 ` Boris Brezillon
2019-08-25 13:08 ` Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 4/7] mtd: spi-nor: Split spi_nor_init_params() Tudor.Ambarus
2019-08-25 12:03 ` Boris Brezillon
2019-08-25 12:23 ` Tudor.Ambarus
2019-08-25 12:51 ` Boris Brezillon
2019-08-24 12:00 ` [PATCH v2 5/7] mtd: spi-nor: Create a ->set_4byte() method Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 6/7] mtd: spi-nor: Rework the SPI NOR lock/unlock logic Tudor.Ambarus
2019-08-25 12:26 ` Boris Brezillon
2019-08-25 13:10 ` Tudor.Ambarus
2019-08-24 12:00 ` [PATCH v2 7/7] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
2019-08-25 12:24 ` Boris Brezillon
2019-08-25 12:57 ` Tudor.Ambarus [this message]
2019-08-25 13:22 ` Boris Brezillon
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