From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94439C433F5 for ; Wed, 29 Sep 2021 01:56:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6EA6160EFD for ; Wed, 29 Sep 2021 01:56:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243684AbhI2B6G convert rfc822-to-8bit (ORCPT ); Tue, 28 Sep 2021 21:58:06 -0400 Received: from mga09.intel.com ([134.134.136.24]:3995 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243661AbhI2B6F (ORCPT ); Tue, 28 Sep 2021 21:58:05 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10121"; a="224881061" X-IronPort-AV: E=Sophos;i="5.85,331,1624345200"; d="scan'208";a="224881061" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2021 18:56:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,331,1624345200"; d="scan'208";a="655329177" Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by orsmga005.jf.intel.com with ESMTP; 28 Sep 2021 18:56:24 -0700 Received: from orsmsx612.amr.corp.intel.com (10.22.229.25) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 28 Sep 2021 18:56:24 -0700 Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by ORSMSX612.amr.corp.intel.com (10.22.229.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 28 Sep 2021 18:56:23 -0700 Received: from orsmsx611.amr.corp.intel.com ([10.22.229.24]) by ORSMSX611.amr.corp.intel.com ([10.22.229.24]) with mapi id 15.01.2242.012; Tue, 28 Sep 2021 18:56:23 -0700 From: "Yu, Fenghua" To: "Luck, Tony" CC: "Hansen, Dave" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "Peter Zijlstra (Intel)" , Lu Baolu , Joerg Roedel , Josh Poimboeuf , "Jiang, Dave" , "Pan, Jacob jun" , "Raj, Ashok" , "Shankar, Ravi V" , "iommu@lists.linux-foundation.org" , "the arch/x86 maintainers" , Linux Kernel Mailing List Subject: RE: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Thread-Topic: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Thread-Index: AQHXrlpps8sdI0y1ikyhBinC7AfU6auyuuKAgAYjzwCAAC8cgIABPj0AgAAIFQCAABNJgIAAB6kAgAAlrYD//5XdAIAAeikA//+nYIA= Date: Wed, 29 Sep 2021 01:56:23 +0000 Message-ID: <840148c7b70f4358852c4f1ccbc5d567@intel.com> References: <20210920192349.2602141-5-fenghua.yu@intel.com> <1aae375d-3cd4-4ab8-9c64-9e387916e6c0@www.fastmail.com> <035290e6-d914-a113-ea6c-e845d71069cf@intel.com> <3f97b77e-a609-997b-3be7-f44ff7312b0d@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.200.16 x-originating-ip: [10.1.200.100] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Tony, > void *begin_update_one_xsave_feature(struct task_struct *tsk, > enum xfeature xfeature, bool full) { > struct xregs_state *xsave = &tsk->thread.fpu.state.xsave; > struct xregs_state *xinit = &init_fpstate.xsave; > u64 fmask = 1ull << xfeature; > void *addr; > > BUG_ON(!(xsave->header.xcomp_bv & fmask)); > > fpregs_lock(); > > addr = __raw_xsave_addr(xsave, xfeature); > > if (full || tsk != current) { > memcpy(addr, __raw_xsave_addr(xinit, xfeature), > xstate_sizes[xfeature]); > goto out; > } > > if (!(xsave->header.xfeatures & fmask)) { > xsave->header.xfeatures |= fmask; //<<<<< > xsaves(xsave, fmask); > } I'm not sure why the FPU state is initialized here. For updating the PASID state, it's unnecessary to init the PASID state. Maybe it is necessary in other cases? > > out: > xsave->header.xfeatures |= fmask; Setting the xfeatures bit plus updating the PASID state is enough to restore the PASID state to the IA32_PASID MSR. > return addr; > } > > void finish_update_one_xsave_feature(struct task_struct *tsk) { > set_ti_thread_flag(task_thread_info(tsk), TIF_NEED_FPU_LOAD); > if (tsk == current) //<<<<< > __cpu_invalidate_fpregs_state(); //<<<<< > fpregs_unlock(); > } Thanks. -Fenghua