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From: Paul Cercueil <paul@crapouillou.net>
To: 周琰杰 <zhouyanjie@wanyeetech.com>
Cc: tsbogend@alpha.franken.de, mturquette@baylibre.com,
	sboyd@kernel.org, robh+dt@kernel.org, linux-mips@vger.kernel.org,
	devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org, dongsheng.qiu@ingenic.com,
	aric.pzqi@ingenic.com, rick.tyliu@ingenic.com,
	sihui.liu@ingenic.com, jun.jiang@ingenic.com,
	sernia.zhou@foxmail.com
Subject: Re: [PATCH v4 5/5] MIPS: CI20: Add second percpu timer for SMP.
Date: Wed, 30 Jun 2021 13:24:08 +0100	[thread overview]
Message-ID: <84LIVQ.EPXA43L4WLUK@crapouillou.net> (raw)
In-Reply-To: <1624688321-69131-6-git-send-email-zhouyanjie@wanyeetech.com>

Hi Zhou,

Le sam., juin 26 2021 at 14:18:41 +0800, 周琰杰 (Zhou Yanjie) 
<zhouyanjie@wanyeetech.com> a écrit :
> 1.Add a new TCU channel as the percpu timer of core1, this is to
>   prepare for the subsequent SMP support. The newly added channel
>   will not adversely affect the current single-core state.
> 2.Adjust the position of TCU node to make it consistent with the
>   order in jz4780.dtsi file.
> 
> Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

Again, you should avoid moving nodes like that.

Not sure it's worth asking for a v5, so:
Acked-by: Paul Cercueil <paul@crapouillou.net>

Cheers,
-Paul

> ---
> 
> Notes:
>     v2:
>     New patch.
> 
>     v2->v3:
>     No change.
> 
>     v3->v4:
>     Improve TCU related notes.
> 
>  arch/mips/boot/dts/ingenic/ci20.dts | 24 ++++++++++++++----------
>  1 file changed, 14 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts 
> b/arch/mips/boot/dts/ingenic/ci20.dts
> index 3a4eaf1..61c153b 100644
> --- a/arch/mips/boot/dts/ingenic/ci20.dts
> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> @@ -118,6 +118,20 @@
>  	assigned-clock-rates = <48000000>;
>  };
> 
> +&tcu {
> +	/*
> +	 * 750 kHz for the system timers and clocksource,
> +	 * use channel #0 and #1 for the per cpu system timers,
> +	 * and use channel #2 for the clocksource.
> +	 *
> +	 * 3000 kHz for the OST timer to provide a higher
> +	 * precision clocksource.
> +	 */
> +	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
> +					  <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
> +	assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>;
> +};
> +
>  &mmc0 {
>  	status = "okay";
> 
> @@ -522,13 +536,3 @@
>  		bias-disable;
>  	};
>  };
> -
> -&tcu {
> -	/*
> -	 * 750 kHz for the system timer and clocksource,
> -	 * use channel #0 for the system timer, #1 for the clocksource.
> -	 */
> -	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
> -					  <&tcu TCU_CLK_OST>;
> -	assigned-clock-rates = <750000>, <750000>, <3000000>;
> -};
> --
> 2.7.4
> 



  reply	other threads:[~2021-06-30 12:24 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-26  6:18 [PATCH v4 0/5] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
2021-06-26  6:18 ` [PATCH v4 1/5] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
2021-06-26  6:18 ` [PATCH v4 2/5] dt-bindings: clock: Add documentation for MAC PHY control bindings 周琰杰 (Zhou Yanjie)
2021-06-28  2:52   ` Stephen Boyd
2021-06-28  4:46     ` 周琰杰
2021-06-26  6:18 ` [PATCH v4 3/5] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-06-26  6:18 ` [PATCH v4 4/5] MIPS: CI20: Reduce clocksource to 750 kHz 周琰杰 (Zhou Yanjie)
2021-06-30 12:21   ` Paul Cercueil
2021-06-26  6:18 ` [PATCH v4 5/5] MIPS: CI20: Add second percpu timer for SMP 周琰杰 (Zhou Yanjie)
2021-06-30 12:24   ` Paul Cercueil [this message]
2021-07-02 12:04     ` Zhou Yanjie
2021-06-30 12:37 ` [PATCH v4 0/5] Misc Ingenic patches Thomas Bogendoerfer

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