From: Dilip Kota <eswara.kota@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@intel.com>
Cc: gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com,
andrew.murray@arm.com, helgaas@kernel.org, jingoohan1@gmail.com,
robh@kernel.org, martin.blumenstingl@googlemail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, cheol.yong.kim@intel.com,
chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com
Subject: Re: [PATCH v8 2/3] dwc: PCI: intel: PCIe RC controller driver
Date: Thu, 21 Nov 2019 16:52:16 +0800 [thread overview]
Message-ID: <8545714b-9393-3272-9d58-35a91d1681cf@linux.intel.com> (raw)
In-Reply-To: <20191120130826.GM32742@smile.fi.intel.com>
On 11/20/2019 9:08 PM, Andy Shevchenko wrote:
> On Wed, Nov 20, 2019 at 03:43:01PM +0800, Dilip Kota wrote:
>> Add support to PCIe RC controller on Intel Gateway SoCs.
>> PCIe controller is based of Synopsys DesignWare PCIe core.
>>
>> Intel PCIe driver requires Upconfigure support, Fast Training
>> Sequence and link speed configurations. So adding the respective
>> helper functions in the PCIe DesignWare framework.
>> It also programs hardware autonomous speed during speed
>> configuration so defining it in pci_regs.h.
>> +static void pcie_app_wr_mask(struct intel_pcie_port *lpp,
>> + u32 ofs, u32 mask, u32 val)
> It seems your editor is misconfigured. First line should be
>
> static void pcie_app_wr_mask(struct intel_pcie_port *lpp, u32 ofs,
>
> in case you would like to split it logically.
>
>> +static void pcie_rc_cfg_wr_mask(struct intel_pcie_port *lpp,
>> + u32 ofs, u32 mask, u32 val)
> Ditto.
>
>> + pcie_app_wr(lpp, PCIE_APP_IRNCR, PCIE_APP_IRN_INT);
> Extra white space.
My bad, typo error. Will fix them all in the next patch version.
Regards,
Dilip
>
next prev parent reply other threads:[~2019-11-21 8:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-20 7:42 [PATCH v8 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Dilip Kota
2019-11-20 7:42 ` Dilip Kota
2019-11-20 7:43 ` [PATCH v8 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller Dilip Kota
2019-11-20 7:43 ` [PATCH v8 2/3] dwc: PCI: intel: PCIe RC controller driver Dilip Kota
2019-11-20 13:08 ` Andy Shevchenko
2019-11-21 8:52 ` Dilip Kota [this message]
2019-11-20 7:43 ` [PATCH v8 3/3] PCI: artpec6: Configure FTS with dwc helper function Dilip Kota
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8545714b-9393-3272-9d58-35a91d1681cf@linux.intel.com \
--to=eswara.kota@linux.intel.com \
--cc=andrew.murray@arm.com \
--cc=andriy.shevchenko@intel.com \
--cc=cheol.yong.kim@intel.com \
--cc=chuanhua.lei@linux.intel.com \
--cc=devicetree@vger.kernel.org \
--cc=gustavo.pimentel@synopsys.com \
--cc=helgaas@kernel.org \
--cc=jingoohan1@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=martin.blumenstingl@googlemail.com \
--cc=qi-ming.wu@intel.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).