From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C150FA373D for ; Fri, 21 Oct 2022 18:09:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229933AbiJUSJF (ORCPT ); Fri, 21 Oct 2022 14:09:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230038AbiJUSJA (ORCPT ); Fri, 21 Oct 2022 14:09:00 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A19FF26B4BF; Fri, 21 Oct 2022 11:08:59 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0929361E43; Fri, 21 Oct 2022 18:08:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 68869C433D6; Fri, 21 Oct 2022 18:08:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666375738; bh=ya2i1BGerPY7oRYU45apweeFf04fDn3vk6rclZZxgsU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ZQqceF3ZiCq7uFfuUiBuabJ4eYJ6ZzEN5n5fTRFHpUuu0dXRcAHiVHm3rjw0FUwmT hZq6CsCW0++LVPP/FoIuYpfBP4XOsMrf5nAihewaQs3DKeslLO4I+xqr3TO7Z4a6Th POLdyrXBUR9/Nhj4XrDXlx+iURCgcPNvTXKbzhgnO4afo8j/0KrnfquAC6L4TuyThv fdV1kKAYIau+dxvhymRodF1+hRKY7LDTlQk1LIkbIUMlbdCNYN6G6QjeQArsWswr0H nk682eqXz8BhtXw6aFZHUQGWaoJYiSfA9jgywzjsfe37bF3hEqrHve5T/3qQP5he8p mq4robKotUtew== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1olwS0-000ahu-4F; Fri, 21 Oct 2022 19:08:56 +0100 Date: Fri, 21 Oct 2022 19:08:50 +0100 Message-ID: <864jvxnj65.wl-maz@kernel.org> From: Marc Zyngier To: Joe Korty Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] arm64: arch_timer: XGene-1 has 31 bit, not 32 bit, arch timer. In-Reply-To: <20221021153424.GA25677@zipoli.concurrent-rt.com> References: <20221021153424.GA25677@zipoli.concurrent-rt.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: joe.korty@concurrent-rt.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 21 Oct 2022 16:34:24 +0100, Joe Korty wrote: > > arm64: XGene-1 has a 31 bit, not a 32 bit, arch timer. > > Fixes: 012f188504528b8cb32f441ac3bd9ea2eba39c9e ("clocksource/drivers/arm_arch_timer: > Work around broken CVAL implementations") Sorry, but you'll have to provide a bit more of an analysis here. As far as I can tell, you're just changing a parameter without properly describing what breaks and how. > > Testing: > On an 8-cpu Mustang, the following sequence no longer locks up the system: > > echo 0 >/proc/sys/kernel/watchdog > for i in {0..7}; do taskset -c $i echo hi there $i; done > > Stable: > To be applied to 5.16 and above, once accepted by mainline. > > Signed-off-by: Joe Korty > > Index: b/drivers/clocksource/arm_arch_timer.c > =================================================================== > --- a/drivers/clocksource/arm_arch_timer.c > +++ b/drivers/clocksource/arm_arch_timer.c > @@ -805,7 +805,7 @@ static u64 __arch_timer_check_delta(void > const struct midr_range broken_cval_midrs[] = { > /* > * XGene-1 implements CVAL in terms of TVAL, meaning > - * that the maximum timer range is 32bit. Shame on them. > + * that the maximum timer range is 31bit. Shame on them. > */ > MIDR_ALL_VERSIONS(MIDR_CPU_MODEL(ARM_CPU_IMP_APM, > APM_CPU_PART_POTENZA)), > @@ -813,8 +813,8 @@ static u64 __arch_timer_check_delta(void > }; > > if (is_midr_in_range_list(read_cpuid_id(), broken_cval_midrs)) { > - pr_warn_once("Broken CNTx_CVAL_EL1, limiting width to 32bits"); > - return CLOCKSOURCE_MASK(32); > + pr_warn_once("Broken CNTx_CVAL_EL1, limiting width to 31bits"); > + return CLOCKSOURCE_MASK(31); > } > #endif > return CLOCKSOURCE_MASK(arch_counter_get_width()); > Also, this isn't much of a patch. Please see the documentation on how to properly submit one. Thanks, M. -- Without deviation from the norm, progress is not possible.