From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0B46C2D0C0 for ; Sun, 22 Dec 2019 12:22:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9992220665 for ; Sun, 22 Dec 2019 12:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1577017336; bh=yPQ2iDk8i9fBF7Ai66tYzKFmHDWSebI55CQ4nG1i2k4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=FYemlo6SmmEKsfy8R1T3JBFF1GNq9+2fuHFW7TwDt7cBMFNT1TmX0lKKt7abJOIs4 ZjABxoWw+TcVr0Xg6SO+mB6s6gu20nXY6u+TiNYPJqGkvteuBh8+gPIsh3j2GtQdKb Galc9FCpBv3tyvnDKQmbuMrVLcEvKB+UcJcf1zwI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726709AbfLVMWP (ORCPT ); Sun, 22 Dec 2019 07:22:15 -0500 Received: from inca-roads.misterjones.org ([213.251.177.50]:44611 "EHLO inca-roads.misterjones.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726267AbfLVMWP (ORCPT ); Sun, 22 Dec 2019 07:22:15 -0500 Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=big-swifty.misterjones.org) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:AES256-GCM-SHA384:256) (Exim 4.80) (envelope-from ) id 1ij0FP-00083P-Rq; Sun, 22 Dec 2019 13:22:12 +0100 Date: Sun, 22 Dec 2019 12:22:10 +0000 Message-ID: <864kxsim8d.wl-maz@kernel.org> From: Marc Zyngier To: Andrew Murray Cc: kvm@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Sudeep Holla , will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 00/18] arm64: KVM: add SPE profiling support In-Reply-To: References: <20191220143025.33853-1-andrew.murray@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: andrew.murray@arm.com, kvm@vger.kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, sudeep.holla@arm.com, will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 21 Dec 2019 10:48:16 +0000, Marc Zyngier wrote: > > [fixing email addresses] > > Hi Andrew, > > On 2019-12-20 14:30, Andrew Murray wrote: > > This series implements support for allowing KVM guests to use the Arm > > Statistical Profiling Extension (SPE). > > Thanks for this. In future, please Cc me and Will on email addresses > we can actually read. > > > It has been tested on a model to ensure that both host and guest can > > simultaneously use SPE with valid data. E.g. > > > > $ perf record -e arm_spe/ts_enable=1,pa_enable=1,pct_enable=1/ \ > > dd if=/dev/zero of=/dev/null count=1000 > > $ perf report --dump-raw-trace > spe_buf.txt > > > > As we save and restore the SPE context, the guest can access the SPE > > registers directly, thus in this version of the series we remove the > > trapping and emulation. > > > > In the previous series of this support, when KVM SPE isn't > > supported (e.g. via CONFIG_KVM_ARM_SPE) we were able to return a > > value of 0 to all reads of the SPE registers - as we can no longer > > do this there isn't a mechanism to prevent the guest from using > > SPE - thus I'm keen for feedback on the best way of resolving > > this. > > Surely there is a way to conditionally trap SPE registers, right? You > should still be able to do this if SPE is not configured for a given > guest (as we do for other feature such as PtrAuth). > > > It appears necessary to pin the entire guest memory in order to > > provide guest SPE access - otherwise it is possible for the guest > > to receive Stage-2 faults. > > Really? How can the guest receive a stage-2 fault? This doesn't fit > what I understand of the ARMv8 exception model. Or do you mean a SPE > interrupt describing a S2 fault? > > And this is not just pinning the memory either. You have to ensure that > all S2 page tables are created ahead of SPE being able to DMA to guest > memory. This may have some impacts on the THP code... > > I'll have a look at the actual series ASAP (but that's not very soon). I found some time to go through the series, and there is clearly a lot of work left to do: - There so nothing here to handle memory pinning whatsoever. If it works, it is only thanks to some side effect. - The missing trapping is deeply worrying. Given that this is an optional feature, you cannot just let the guest do whatever it wants in an uncontrolled manner. - The interrupt handling is busted. You mix concepts picked from both the PMU and the timer code, while the SPE device doesn't behave like any of these two (it is neither a fully emulated device, nor a device that is exclusively owned by a guest at any given time). I expect some level of discussion on the list including at least Will and myself before you respin this. M. -- Jazz is not dead, it just smells funny.