From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E53AFC43381 for ; Tue, 2 Apr 2019 05:00:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B8BA220674 for ; Tue, 2 Apr 2019 05:00:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728661AbfDBFAu (ORCPT ); Tue, 2 Apr 2019 01:00:50 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:44688 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725778AbfDBFAt (ORCPT ); Tue, 2 Apr 2019 01:00:49 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1B21CA78; Mon, 1 Apr 2019 22:00:49 -0700 (PDT) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 34B013F59C; Mon, 1 Apr 2019 22:00:46 -0700 (PDT) Date: Tue, 02 Apr 2019 06:00:43 +0100 Message-ID: <86ef6l57d0.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Heyi Guo Cc: , Thomas Gleixner , Jason Cooper , wanghaibin 00208455 Subject: Re: MSI number limit for PCI hotplug under PCI bridge on ARM platform In-Reply-To: <327ba551-2cbd-08bb-d4c1-107c3ff7d45d@huawei.com> References: <327ba551-2cbd-08bb-d4c1-107c3ff7d45d@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 01 Apr 2019 14:55:52 +0100, Heyi Guo wrote: > > Hi folks, > > In current kernel implementation for ARM platform, all devices under > one PCI bridge share a same device ID and the total number of MSI > interrupts is fixed at the first time any child device is allocating > MSI. However, this may cause failure of allocating MSI if the system > supports device hot-plug under the PCI bridge, which is possible for > ARM virtual machine with generic pcie-to-pci-bridge and kernel > config HOTPLUG_PCI_SHPC enabled. > > Does it make sense to add support for the above scenario? If it > does, any suggestion for how to do that? I don't think it makes much sense. You have the flexibility not to add such a broken setup to your guests, and instead have enough pcie ports so that you can always have an exact allocation and no DevID aliasing. The alternative is to dynamically grow the ITT for a given DevID, which cannot be done without unmapping it first. This in turn will result in interrupts being lost while the DevID was unmapped, and they'd need to be pessimistically reinjected. This also involves a substantial amount of data structure repainting, as you're pretty much guaranteed not to be able to reuse the same LPI range. Given that this is arbitrarily self-inflicted, I'm not overly keen on even trying to support this. Thanks, M. -- Jazz is not dead, it just smell funny.