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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id j123sm21766217wmb.32.2019.05.27.09.12.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 May 2019 09:12:45 -0700 (PDT) From: Loys Ollivier To: Atish Patra Cc: Kevin Hilman , Paul Walmsley , "linux-kernel\@vger.kernel.org" , "linux-serial\@vger.kernel.org" , "linux-riscv\@lists.infradead.org" , "gregkh\@linuxfoundation.org" Subject: Re: [PATCH v5 0/2] tty: serial: add DT bindings and serial driver for the SiFive FU540 UART References: <20190413020111.23400-1-paul.walmsley@sifive.com> <7hmukmew5j.fsf@baylibre.com> <883f3d5f-9b04-1435-30d3-2b48ab7eb76d@wdc.com> Date: Mon, 27 May 2019 18:12:43 +0200 In-Reply-To: <883f3d5f-9b04-1435-30d3-2b48ab7eb76d@wdc.com> (Atish Patra's message of "Thu, 18 Apr 2019 18:04:34 -0700") Message-ID: <86sgszq3k4.fsf@baylibre.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu 18 Apr 2019 at 18:04, Atish Patra wrote: > On 4/18/19 4:22 PM, Kevin Hilman wrote: >> Hi Paul, >> >> Paul Walmsley writes: >> >>> This series adds a serial driver, with console support, for the >>> UART IP block present on the SiFive FU540 SoC. The programming >>> model is straightforward, but unique. >>> >>> Boot-tested on a SiFive FU540 HiFive-U board, using BBL and the >>> open-source FSBL (with appropriate patches to the DT data). >>> >>> This fifth version fixes a bug in the set_termios handler, >>> found by Andreas Schwab . >>> >>> The patches in this series can also be found, with the PRCI patches, >>> DT patches, and DT prerequisite patch, at: >>> >>> https://github.com/sifive/riscv-linux/tree/dev/paulw/serial-v5.1-rc4 >> >> I tried this branch, and it doesn't boot on my unleashed board. >> >> Here's the boot log when I pass the DT built from your branch via >> u-boot: https://termbin.com/rfp3. >> > > Unfortunately, that won't work. The current DT modifications by OpenSBI. > > 1. Change hart status to "masked" from "okay". > 2. M-mode interrupt masking in PLIC node. > 3. Add a chosen node for serial access in U-Boot. > > You can ignore 3 for your use case. However, if you pass a dtb built from source > code, that will have hart0 enabled and M-mode interrupts enabled in DT. Atish, I'm trying to get the kernel boot with the current linux kernel DT from Paul's patch series [0]. Could you point me to some documentation on 2. ? Or do you know of a way to disable M-mode interrupts from U-boot ? [0]: https://lore.kernel.org/patchwork/project/lkml/list/?series=390077 Thanks, Loys > > Not sure if we should do these DT modifications in U-Boot as well. >