From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A937DC63793 for ; Thu, 22 Jul 2021 15:12:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 82CFB6109D for ; Thu, 22 Jul 2021 15:12:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232493AbhGVOcF (ORCPT ); Thu, 22 Jul 2021 10:32:05 -0400 Received: from mail.kernel.org ([198.145.29.99]:59620 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232317AbhGVObr (ORCPT ); Thu, 22 Jul 2021 10:31:47 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 647B861029; Thu, 22 Jul 2021 15:12:22 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1m6aN2-000I4e-BE; Thu, 22 Jul 2021 16:12:20 +0100 Date: Thu, 22 Jul 2021 16:12:19 +0100 Message-ID: <871r7q2xik.wl-maz@kernel.org> From: Marc Zyngier To: Thomas Gleixner Cc: LKML , Alex Williamson , "Raj, Ashok" , Ingo Molnar , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , x86@kernel.org Subject: Re: [patch 6/8] genirq: Provide IRQCHIP_AFFINITY_PRE_STARTUP In-Reply-To: <20210721192650.687529735@linutronix.de> References: <20210721191126.274946280@linutronix.de> <20210721192650.687529735@linutronix.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tglx@linutronix.de, linux-kernel@vger.kernel.org, alex.williamson@redhat.com, ashok.raj@intel.com, mingo@kernel.org, davem@davemloft.net, bhelgaas@google.com, linux-pci@vger.kernel.org, kevin.tian@intel.com, x86@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 21 Jul 2021 20:11:32 +0100, Thomas Gleixner wrote: > > X86 IO/APIC and MSI interrupts (when used without interrupts remapping) > require that the affinity setup on startup is done before the interrupt is > enabled for the first time as the non-remapped operation mode cannot safely > migrate enabled interrupts from arbitrary contexts. Provide a new irq chip > flag which allows affected hardware to request this. > > This has to be opt-in because there have been reports in the past that some > interrupt chips cannot handle affinity setting before startup. > > Fixes: 18404756765c ("genirq: Expose default irq affinity mask (take 3)") > Signed-off-by: Thomas Gleixner > Cc: Thomas Gleixner > Cc: Marc Zyngier > Cc: Ingo Molnar > --- > include/linux/irq.h | 2 ++ > kernel/irq/chip.c | 5 ++++- > 2 files changed, 6 insertions(+), 1 deletion(-) > > --- a/include/linux/irq.h > +++ b/include/linux/irq.h > @@ -569,6 +569,7 @@ struct irq_chip { > * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips > * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs > * in the suspend path if they are in disabled state > + * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup > */ > enum { > IRQCHIP_SET_TYPE_MASKED = (1 << 0), > @@ -581,6 +582,7 @@ enum { > IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), > IRQCHIP_SUPPORTS_NMI = (1 << 8), > IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), > + IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10), > }; > > #include > --- a/kernel/irq/chip.c > +++ b/kernel/irq/chip.c > @@ -265,8 +265,11 @@ int irq_startup(struct irq_desc *desc, b > } else { > switch (__irq_startup_managed(desc, aff, force)) { > case IRQ_STARTUP_NORMAL: > + if (d->chip->flags & IRQCHIP_AFFINITY_PRE_STARTUP) > + irq_setup_affinity(desc); How about moving this to activate instead? We already special-case the activation of MSIs for PCI (MSI_FLAG_ACTIVATE_EARLY), and this wouldn't look completely out of place. The startup mode could be an issue though... > ret = __irq_startup(desc); > - irq_setup_affinity(desc); > + if (!(d->chip->flags & IRQCHIP_AFFINITY_PRE_STARTUP)) > + irq_setup_affinity(desc); > break; > case IRQ_STARTUP_MANAGED: > irq_do_set_affinity(d, aff, false); Otherwise, looks good. M. -- Without deviation from the norm, progress is not possible.