From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63639C433F5 for ; Wed, 16 Mar 2022 15:37:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346508AbiCPPiO (ORCPT ); Wed, 16 Mar 2022 11:38:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242953AbiCPPiN (ORCPT ); Wed, 16 Mar 2022 11:38:13 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A05606D1B0 for ; Wed, 16 Mar 2022 08:36:58 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2ECCA6160B for ; Wed, 16 Mar 2022 15:36:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87F51C340E9; Wed, 16 Mar 2022 15:36:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1647445017; bh=yB9AJOgY4sOTPrFxr8a/h8XcUZfs27iFeh3/dqiV4dM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=lj1avmWrVAztkAfvUGT6/CZexumbiWZpWi2zCuvkfNXdKT2oEPetW4kkHGC9xii+0 BeWilsa7XdW+T6QR8SStRavIVerkxUMxccJtWl3i1GaV7vDTfbtdLKYAgS4b9FuHZ0 fh8Uk5+Jb3g46gpS63DjmbMpEmuWJDIdvekeFFnGEuAn6+XtXkeST9gU9L5ZNI9hR9 IzsStFDT0Of3kGUC5Ea2Qkeh27JO/FXsmVGSo6tJQl01ZqBWvDH6e2uHjALcTWfXIM zdBBdd6VsayLZlV93+x5zcQvB2mqSFBgU1XeAIglL3kdickUBXfE1e/gdsNX/3kq6O lPI/YG0Ugs+cQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nUVhn-00ExZY-32; Wed, 16 Mar 2022 15:36:55 +0000 Date: Wed, 16 Mar 2022 15:36:54 +0000 Message-ID: <8735jhzz6x.wl-maz@kernel.org> From: Marc Zyngier To: Andre Przywara Cc: linux-kernel@vger.kernel.org, Lorenzo Pieralisi , Thomas Gleixner , Eric Auger , Oliver Upton Subject: Re: [PATCH 2/3] irqchip/gic-v3: Detect LPI invalidation MMIO registers In-Reply-To: <20220316145141.44d20486@slackpad.lan> References: <20220315165034.794482-1-maz@kernel.org> <20220315165034.794482-3-maz@kernel.org> <20220316145141.44d20486@slackpad.lan> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: andre.przywara@arm.com, linux-kernel@vger.kernel.org, lorenzo.pieralisi@arm.com, tglx@linutronix.de, eric.auger@redhat.com, oupton@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 16 Mar 2022 14:51:58 +0000, Andre Przywara wrote: > > On Tue, 15 Mar 2022 16:50:33 +0000 > Marc Zyngier wrote: > > Hi, > > > Since GICv4.1, an implementation can offer the same MMIO-based > > implementation as DirectLPI, only with an ITS. Given that this > > can be hugely beneficial for workloads that are very LPI masking > > heavy (although these workloads are admitedly a bit odd). > > > > Interestingly, this is independent of RVPEI, which only *implies* > > the functionnality. > > > > So let's detect whether the implementation has GICR_CTLR.IR set, > > and propagate this as DirectLPI to the ITS driver. > > > > Signed-off-by: Marc Zyngier > > --- > > drivers/irqchip/irq-gic-v3.c | 15 +++++++++++---- > > include/linux/irqchip/arm-gic-v3.h | 2 ++ > > 2 files changed, 13 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > > index 736163d36b13..363bfe172033 100644 > > --- a/drivers/irqchip/irq-gic-v3.c > > +++ b/drivers/irqchip/irq-gic-v3.c > > @@ -918,7 +918,11 @@ static int gic_populate_rdist(void) > > static int __gic_update_rdist_properties(struct redist_region *region, > > void __iomem *ptr) > > { > > - u64 typer = gic_read_typer(ptr + GICR_TYPER); > > + u64 typer; > > + u32 ctlr; > > + > > + typer = gic_read_typer(ptr + GICR_TYPER); > > + ctlr = readl_relaxed(ptr + GICR_CTLR); > > Is there any reason you didn't keep this together? I thought this was > recommended, in general? Sorry, keep what together with what? > > > > > /* Boot-time cleanip */ > > if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) { > > @@ -941,6 +945,7 @@ static int __gic_update_rdist_properties(struct redist_region *region, > > /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ > > gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID); > > gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) | > > + !!(ctlr & GICR_CTLR_IR) | > > So this means that has_direct_lpi is not really correct anymore, as the > IR bit only covers the INVL and SYNCR registers, not the GICR_SETLPIR > and GICR_CLRLPIR registers, if I understand the spec correctly? > > But I guess this is nitpicking, as we don't use direct LPIs at all in > Linux? And I guess the target is lpi_update_config(), which now doesn't > need the command queue anymore? Exactly. The history of this crap is convoluted: The canonical goal of DirectLPI was to support LPIs without an ITS. Thankfully, this was never implemented. What was implemented by our HiSi friends was DirectLPI *with* an ITS, which was illegal at the time, but also the only way to make GICv4.0 work at a reasonable speed. That's where the direct_lpi boolean comes from. RVPEI added some more confusion by offering a subset of DirectLPI for invalidation of vlpis. And then IR was introduced because there is really no reason not to offer the same service on GICv3. > > Maybe this could be clarified in the commit message? Sure, can do. > > > gic_data.rdists.has_rvpeid); > > gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY); > > > > @@ -962,7 +967,11 @@ static void gic_update_rdist_properties(void) > > gic_iterate_rdists(__gic_update_rdist_properties); > > if (WARN_ON(gic_data.ppi_nr == UINT_MAX)) > > gic_data.ppi_nr = 0; > > - pr_info("%d PPIs implemented\n", gic_data.ppi_nr); > > + pr_info("GICv3 features: %d PPIs, %s%s\n", > > I like having that on one line, but it looks a bit odd with the > trailing comma when we have neither RSS nor DirectLPI. > What about: > pr_info("GICv3 features: %d PPIs%s%s\n", > gic_data.ppi_nr, > gic_data.has_rss ? ", RSS" : "", > gic_data.rdists.has_direct_lpi ? ", DirectLPI" : ""); Yeah, looks better. Thanks, M. -- Without deviation from the norm, progress is not possible.