From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F8A8C07E96 for ; Tue, 6 Jul 2021 13:21:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 21CD161C1E for ; Tue, 6 Jul 2021 13:21:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232004AbhGFNXu (ORCPT ); Tue, 6 Jul 2021 09:23:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:35550 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231771AbhGFNXt (ORCPT ); Tue, 6 Jul 2021 09:23:49 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0E49861A19; Tue, 6 Jul 2021 13:21:11 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1m0l0e-00BjmO-R9; Tue, 06 Jul 2021 14:21:09 +0100 Date: Tue, 06 Jul 2021 14:21:08 +0100 Message-ID: <8735sr8tob.wl-maz@kernel.org> From: Marc Zyngier To: Huacai Chen Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang Subject: Re: [PATCH 7/9] irqchip: Add LoongArch CPU interrupt controller support In-Reply-To: <20210706030904.1411775-8-chenhuacai@loongson.cn> References: <20210706030904.1411775-1-chenhuacai@loongson.cn> <20210706030904.1411775-8-chenhuacai@loongson.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: chenhuacai@loongson.cn, tglx@linutronix.de, linux-kernel@vger.kernel.org, lixuefeng@loongson.cn, chenhuacai@gmail.com, jiaxun.yang@flygoat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 06 Jul 2021 04:09:02 +0100, Huacai Chen wrote: > > We are preparing to add new Loongson (based on LoongArch, not MIPS) > support. This patch add LoongArch CPU interrupt controller support. > > Signed-off-by: Huacai Chen > --- > drivers/irqchip/Kconfig | 10 ++++ > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-loongarch-cpu.c | 87 +++++++++++++++++++++++++++++ > 3 files changed, 98 insertions(+) > create mode 100644 drivers/irqchip/irq-loongarch-cpu.c > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > index 084bc4c2eebd..443c3a7a0cc1 100644 > --- a/drivers/irqchip/Kconfig > +++ b/drivers/irqchip/Kconfig > @@ -528,6 +528,16 @@ config EXYNOS_IRQ_COMBINER > Say yes here to add support for the IRQ combiner devices embedded > in Samsung Exynos chips. > > +config IRQ_LOONGARCH_CPU > + bool > + select GENERIC_IRQ_CHIP > + select IRQ_DOMAIN > + select GENERIC_IRQ_EFFECTIVE_AFF_MASK > + help > + Support for the LoongArch CPU Interrupt Controller. For details of > + irq chip hierarchy on LoongArch platforms please read the document > + Documentation/loongarch/irq-chip-model.rst. > + > config LOONGSON_LIOINTC > bool "Loongson Local I/O Interrupt Controller" > depends on MACH_LOONGSON64 > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > index f88cbf36a9d2..4e34eebe180b 100644 > --- a/drivers/irqchip/Makefile > +++ b/drivers/irqchip/Makefile > @@ -105,6 +105,7 @@ obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o > obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o > obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o > obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o > +obj-$(CONFIG_IRQ_LOONGARCH_CPU) += irq-loongarch-cpu.o > obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o > obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o > obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o > diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c > new file mode 100644 > index 000000000000..918d61a5a980 > --- /dev/null > +++ b/drivers/irqchip/irq-loongarch-cpu.c > @@ -0,0 +1,87 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Loongson Technologies, Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +static struct irq_domain *irq_domain; > + > +static inline void unmask_loongarch_irq(struct irq_data *d) > +{ > + set_csr_ecfg(ECFGF(d->hwirq)); > +} > + > +static inline void mask_loongarch_irq(struct irq_data *d) > +{ > + clear_csr_ecfg(ECFGF(d->hwirq)); > +} > + > +#define enable_loongarch_irq unmask_loongarch_irq > +#define disable_loongarch_irq mask_loongarch_irq > + > +static struct irq_chip loongarch_cpu_irq_controller = { > + .name = "LoongArch", > + .irq_ack = mask_loongarch_irq, > + .irq_mask = mask_loongarch_irq, > + .irq_mask_ack = mask_loongarch_irq, > + .irq_unmask = unmask_loongarch_irq, > + .irq_eoi = unmask_loongarch_irq, > + .irq_enable = enable_loongarch_irq, > + .irq_disable = disable_loongarch_irq, NAK. Clearly, you don't understand what these callbacks do. > +}; > + > +asmlinkage void __weak plat_irq_dispatch(int irq) > +{ > + do_IRQ(irq_linear_revmap(irq_domain, irq)); > +} NAK. If you are going to add a new architecture to Linux, do not mimic the MIPS brain-damage. Have your new architecture to support multiple interrupt controllers from day one without the need to add these silly weak symbols. Move the low-level code such as this into the architecture code, and use the existing domain abstractions. > + > +static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq, > + irq_hw_number_t hwirq) > +{ > + struct irq_chip *chip; > + > + chip = &loongarch_cpu_irq_controller; > + set_vi_handler(EXCCODE_INT_START + hwirq, plat_irq_dispatch); > + irq_set_chip_and_handler(irq, chip, handle_percpu_irq); > + > + return 0; > +} > + > +static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = { > + .map = loongarch_cpu_intc_map, > + .xlate = irq_domain_xlate_onecell, Are all interrupts with the same trigger? > +}; > + > + > +int __init loongarch_cpu_irq_init(struct device_node *of_node, struct device_node *parent) > +{ > + int i; > + > + /* Mask interrupts. */ > + clear_csr_ecfg(ECFG0_IM); > + clear_csr_estat(ESTATF_IP); > + > + irq_alloc_descs(-1, LOONGSON_CPU_IRQ_BASE, EXCCODE_INT_NUM, 0); > + > + for (i = LOONGSON_CPU_IRQ_BASE; i <= LOONGSON_CPU_LAST_IRQ; i++) > + irq_set_noprobe(i); > + > + irq_domain = irq_domain_add_legacy(of_node, EXCCODE_INT_NUM, > + LOONGSON_CPU_IRQ_BASE, 0, &loongarch_cpu_intc_irq_domain_ops, NULL); Oh, the irony of using irq_domain_add_legacy() for a brand new architecture... > + > + if (!irq_domain) > + panic("Failed to add irqdomain for loongarch CPU"); > + > + return 0; > +} > + > +IRQCHIP_DECLARE(cpu_intc, "loongson,cpu-interrupt-controller", loongarch_cpu_irq_init); As it stands, this driver has zero chance of being merged. You seriously need to move your low-level interrupt handling code into the 21st century. M. -- Without deviation from the norm, progress is not possible.