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[91.219.240.2]) by smtp.gmail.com with ESMTPSA id w10sm14914491ejv.44.2020.09.07.01.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2020 01:37:40 -0700 (PDT) From: Vitaly Kuznetsov To: Sean Christopherson Cc: Peter Xu , kvm@vger.kernel.org, Paolo Bonzini , Wanpeng Li , Jim Mattson , Michael Tsirkin , Julia Suvorova , Andy Lutomirski , Andrew Jones , linux-kernel@vger.kernel.org, Gerd Hoffmann Subject: Re: [PATCH v2 0/3] KVM: x86: KVM_MEM_PCI_HOLE memory In-Reply-To: <20200904160008.GA2206@sjchrist-ice> References: <20200807141232.402895-1-vkuznets@redhat.com> <20200825212526.GC8235@xz-x1> <87eenlwoaa.fsf@vitty.brq.redhat.com> <20200901200021.GB3053@xz-x1> <877dtcpn9z.fsf@vitty.brq.redhat.com> <20200904061210.GA22435@sjchrist-ice> <20200904072905.vbkiq3h762fyzds6@sirius.home.kraxel.org> <20200904160008.GA2206@sjchrist-ice> Date: Mon, 07 Sep 2020 10:37:39 +0200 Message-ID: <874koanfsc.fsf@vitty.brq.redhat.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Sean Christopherson writes: > On Fri, Sep 04, 2020 at 09:29:05AM +0200, Gerd Hoffmann wrote: >> Hi, >> >> > Unless I'm mistaken, microvm doesn't even support PCI, does it? >> >> Correct, no pci support right now. >> >> We could probably wire up ecam (arm/virt style) for pcie support, once >> the acpi support for mictovm finally landed (we need acpi for that >> because otherwise the kernel wouldn't find the pcie bus). >> >> Question is whenever there is a good reason to do so. Why would someone >> prefer microvm with pcie support over q35? >> >> > If all of the above is true, this can be handled by adding "pci=lastbus=0" >> > as a guest kernel param to override its scanning of buses. And couldn't >> > that be done by QEMU's microvm_fix_kernel_cmdline() to make it transparent >> > to the end user? >> >> microvm_fix_kernel_cmdline() is a hack, not a solution. >> >> Beside that I doubt this has much of an effect on microvm because >> it doesn't support pcie in the first place. > > I am so confused. Vitaly, can you clarify exactly what QEMU VM type this > series is intended to help? If this is for microvm, then why is the guest > doing PCI scanning in the first place? If it's for q35, why is the > justification for microvm-like workloads? I'm not exactly sure about the plans for particular machine types, the intention was to use this for pcie in QEMU in general so whatever machine type uses pcie will benefit. Now, it seems that we have a more sophisticated landscape. The optimization will only make sense to speed up boot so all 'traditional' VM types with 'traditional' firmware are out of question. 'Container-like' VMs seem to avoid PCI for now, I'm not sure if it's because they're in early stages of their development, because they can get away without PCI or, actually, because of slowness at boot (which we're trying to tackle with this feature). I'd definitely like to hear more what people think about this. > > Either way, I think it makes sense explore other options before throwing > something into KVM, e.g. modifying guest command line, adding a KVM hint, > "fixing" QEMU, etc... > Initially, this feature looked like a small and straitforward (micro-)optimization to me: memory regions with 'PCI hole' semantics do exist and we can speed up access to them. Ideally, I'd like to find other 'constant memory' regions requiring fast access and come up with an interface to create them in KVM but so far nothing interesting came up... -- Vitaly