From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 884BDC432BE for ; Tue, 10 Aug 2021 12:33:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6DD8F60EFF for ; Tue, 10 Aug 2021 12:33:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238649AbhHJMds (ORCPT ); Tue, 10 Aug 2021 08:33:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:39566 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229764AbhHJMdq (ORCPT ); Tue, 10 Aug 2021 08:33:46 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 30FFC60EFF; Tue, 10 Aug 2021 12:33:24 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mDQwc-0043MH-7B; Tue, 10 Aug 2021 13:33:22 +0100 Date: Tue, 10 Aug 2021 13:33:21 +0100 Message-ID: <875ywdbhta.wl-maz@kernel.org> From: Marc Zyngier To: Kishon Vijay Abraham I Cc: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Tom Joseph , , , , , , Lokesh Vutla Subject: Re: [PATCH v2 2/3] PCI: j721e: Add PCI legacy interrupt support for J721E In-Reply-To: <7646c75e-29de-1edc-225c-57feeaa80118@ti.com> References: <20210804132912.30685-1-kishon@ti.com> <20210804132912.30685-3-kishon@ti.com> <87h7g5w8d8.wl-maz@kernel.org> <87o8a7arew.wl-maz@kernel.org> <7646c75e-29de-1edc-225c-57feeaa80118@ti.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kishon@ti.com, bhelgaas@google.com, robh+dt@kernel.org, lorenzo.pieralisi@arm.com, tjoseph@cadence.com, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lokeshvutla@ti.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 09 Aug 2021 15:58:38 +0100, Kishon Vijay Abraham I wrote: > > Hi Marc, > > On 09/08/21 3:09 pm, Marc Zyngier wrote: > > On Mon, 09 Aug 2021 05:50:10 +0100, > > Kishon Vijay Abraham I wrote: > >> > >> Hi Marc, > >> > >> On 04/08/21 8:43 pm, Marc Zyngier wrote: > >>> On Wed, 04 Aug 2021 14:29:11 +0100, > >>> Kishon Vijay Abraham I wrote: > >>>> > >>>> Add PCI legacy interrupt support for J721E. J721E has a single HW > >>>> interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD. > >>>> The HW interrupt line connected to GIC is a pulse interrupt whereas > >>>> the legacy interrupts by definition is level interrupt. In order to > >>>> provide level interrupt functionality to edge interrupt line, PCIe > >>>> in J721E has provided IRQ_EOI register. > >>>> > >>>> However due to Errata ID #i2094 ([1]), EOI feature is not enabled in HW > >>>> and only a single pulse interrupt will be generated for every > >>>> ASSERT_INTx/DEASSERT_INTx. > >>> > >>> So my earlier remark stands. If you get a single edge, how do you > >>> handle a level that is still high after having handled the interrupt > >>> on hardware that has this bug? > >> > >> Right, this hardware (J721E) has a bug but was fixed in J7200 (Patch 3/3 > >> handles that). > > > > But how do you make it work with J721E? Is it even worth supporting if > > (as I expect) it is unreliable? > > I've seen at-least the NVMe devices triggers the interrupts again and > the data transfer completes. But I agree, this is unreliable. Then I don't think you should add INTx support for this system. It is bound to be a support burden, and will reflect badly on the whole platform. Focusing on J7200 is probably the best thing to do. Thanks, M. -- Without deviation from the norm, progress is not possible.