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From: Robert Jarzmik <robert.jarzmik@free.fr>
To: Marek Vasut <marex@denx.de>
Cc: Brian Norris <computersforpeace@gmail.com>,
        Boris Brezillon <boris.brezillon@free-electrons.com>,
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        Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
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        Kyungmin Park <kyungmin.park@samsung.com>,
        Han Xu <han.xu@freescale.com>, Huang Shijie <shijie.huang@arm.com>
Subject: Re: [PATCH 1/5] mtd: ofpart: grab device tree node directly from master device node
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	<201510282347.27379.marex@denx.de>
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Date: Thu, 29 Oct 2015 07:32:33 +0100
In-Reply-To: <201510282347.27379.marex@denx.de> (Marek Vasut's message of
	"Wed, 28 Oct 2015 23:47:27 +0100")
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Marek Vasut <marex@denx.de> writes:

>> Isn't there the case of a single NAND controller with 2 identical chips,
>> each a 8 bit NAND chip, and the controller aggregating them to offer the
>> OS a single 16-bit NAND chip ?
>
> Is that using 1 or 2 physical chipselect lines on the CPU (controller) ?
I think it's 2 physical chipselects (CS0 and CS1). The way I understand it is
that the NAND controller asserts them both, issues the command on the command
line (shared between the 2 chips), and reads/writes on the separate data lines.

Cheers.

-- 
Robert