From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E1BAC433F5 for ; Mon, 24 Jan 2022 14:05:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238446AbiAXOFe (ORCPT ); Mon, 24 Jan 2022 09:05:34 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:59536 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238356AbiAXOFc (ORCPT ); Mon, 24 Jan 2022 09:05:32 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0966EB8100B; Mon, 24 Jan 2022 14:05:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B71D6C340E4; Mon, 24 Jan 2022 14:05:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643033129; bh=6P+R8VnmDB3dT+j9DILXJFZf9Tn9cSGCM1mGeXRYho0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=rTrzNvFbH/iT6SDidIbXnsToidddYd4KHCbVBrwMlAnjf24kRGxRXpCl+Gas/roia woa1jMAwLu86tbWOUdbhGrJgx6sMbjSK2Iz4BpXJZCcU6o/nUyyuHJNSpfDaC6+Rnq x43oripcFvVK3/GVVRoW+r5QGMnzQ5YcJiJPpcCNGGTh27a4jkDMQZvoSMx2gIJ4eA cDSYFD3oMLnib/FbJoEGchdi5bALNSDBDdZQHSBjblihpJrftOhCRZ0CFStsj0F4Ns AZNFQZtkM6f8t4ppYYA/8Mr1jPBVbxXxSjZeRe8f6819Wh/FLg5w3S5z1uYZYgK78u 2IG4fUCJ6LO6w== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nBzyJ-002OpM-OT; Mon, 24 Jan 2022 14:05:27 +0000 Date: Mon, 24 Jan 2022 14:05:27 +0000 Message-ID: <877dap8c0o.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , linux-perf-users@vger.kernel.org Subject: Re: [RFC V1 02/11] arm64/perf: Add register definitions for BRBE In-Reply-To: <1642998653-21377-3-git-send-email-anshuman.khandual@arm.com> References: <1642998653-21377-1-git-send-email-anshuman.khandual@arm.com> <1642998653-21377-3-git-send-email-anshuman.khandual@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 24 Jan 2022 04:30:44 +0000, Anshuman Khandual wrote: > > This adds BRBE related register definitions and various other related field > macros there in. These will be used subsequently in a BRBE driver which is > being added later on. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Marc Zyngier > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > arch/arm64/include/asm/sysreg.h | 216 ++++++++++++++++++++++++++++++++ > 1 file changed, 216 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 898bee0004ae..d8fd7e806a47 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -141,6 +141,218 @@ > #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) > #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) > > +/* > + * BRBINF_EL1 Encoding: [2, 1, 8, CRm, op2] > + * > + * derived as = c{N<3:0>} = (N<4>x4 + 0) > + */ > +#define SYS_BRBINF0_EL1 sys_reg(2, 1, 8, 0, 0) > +#define SYS_BRBINF1_EL1 sys_reg(2, 1, 8, 1, 0) > +#define SYS_BRBINF2_EL1 sys_reg(2, 1, 8, 2, 0) > +#define SYS_BRBINF3_EL1 sys_reg(2, 1, 8, 3, 0) > +#define SYS_BRBINF4_EL1 sys_reg(2, 1, 8, 4, 0) > +#define SYS_BRBINF5_EL1 sys_reg(2, 1, 8, 5, 0) > +#define SYS_BRBINF6_EL1 sys_reg(2, 1, 8, 6, 0) > +#define SYS_BRBINF7_EL1 sys_reg(2, 1, 8, 7, 0) > +#define SYS_BRBINF8_EL1 sys_reg(2, 1, 8, 8, 0) > +#define SYS_BRBINF9_EL1 sys_reg(2, 1, 8, 9, 0) [snip] Since the architecture gives you the formula to build these, why do you enumerate each and every register encoding? I'd rather see something like: #define __SYS_BRBINFO(n) sys_reg(2, 1, 8, ((n) & 0xf), (((n) & 0x10)) >> 2) #define SYS_BRBINF0_EL1 __SYS_BRBINFO(0) [...] and something similar for all the new registers that come in packs of 32... We already have similar things for AMU, PMU, GIC and co. Thanks, M. -- Without deviation from the norm, progress is not possible.