From: Thomas Gleixner <tglx@linutronix.de>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>, maz@kernel.org
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>,
Jason Cooper <jason@lakedaemon.net>,
Rob Herring <robh+dt@kernel.org>, Huacai Chen <chenhc@lemote.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-mips@vger.kernel.org
Subject: Re: [PATCH v2 3/6] irqchip: Add Loongson PCH PIC controller
Date: Wed, 13 May 2020 14:09:09 +0200 [thread overview]
Message-ID: <877dxg3ul6.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20200428063247.2223499-3-jiaxun.yang@flygoat.com>
Jiaxun Yang <jiaxun.yang@flygoat.com> writes:
> +static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit)
> +{
> + void __iomem *addr = priv->base + offset + PIC_REG_IDX(bit) * 4;
> + unsigned long flags;
> + u32 reg;
> +
> + raw_spin_lock_irqsave(&priv->pic_lock, flags);
See other reply.
> + reg = readl(addr);
> + reg |= BIT(PIC_REG_BIT(bit));
> + writel(reg, addr);
> + raw_spin_unlock_irqrestore(&priv->pic_lock, flags);
> +}
> +static int pch_pic_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + struct pch_pic *priv;
> + struct irq_domain *parent_domain;
> + int err;
ordering
Thanks,
tglx
next prev parent reply other threads:[~2020-05-13 12:09 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-22 14:24 [PATCH 0/6] Loongson PCH IRQ Support Jiaxun Yang
2020-04-22 14:24 ` [PATCH 1/6] irqchip: Add Loongson HyperTransport Vector support Jiaxun Yang
2020-04-23 13:31 ` Marc Zyngier
2020-04-22 14:24 ` [PATCH 2/6] dt-bindings: interrupt-controller: Add Loongson HTVEC Jiaxun Yang
2020-04-22 14:24 ` [PATCH 3/6] irqchip: Add Loongson PCH PIC controller Jiaxun Yang
2020-04-23 5:56 ` Huacai Chen
2020-04-23 14:23 ` Marc Zyngier
2020-04-22 14:24 ` [PATCH 4/6] dt-bindings: interrupt-controller: Add Loongson PCH PIC Jiaxun Yang
2020-04-23 5:54 ` Huacai Chen
2020-04-22 14:24 ` [PATCH 5/6] irqchip: Add Loongson PCH MSI controller Jiaxun Yang
2020-04-23 5:57 ` Huacai Chen
2020-04-23 14:41 ` Marc Zyngier
2020-04-24 1:33 ` Jiaxun Yang
2020-04-24 8:28 ` Marc Zyngier
2020-04-22 14:24 ` [PATCH 6/6] dt-bindings: interrupt-controller: Add Loongson PCH MSI Jiaxun Yang
2020-04-23 5:55 ` Huacai Chen
2020-04-23 12:43 ` Marc Zyngier
2020-04-24 1:27 ` Huacai Chen
2020-04-23 5:50 ` [PATCH 0/6] Loongson PCH IRQ Support Huacai Chen
2020-04-28 6:32 ` [PATCH v2 1/6] irqchip: Add Loongson HyperTransport Vector support Jiaxun Yang
2020-04-28 6:32 ` [PATCH v2 2/6] dt-bindings: interrupt-controller: Add Loongson HTVEC Jiaxun Yang
2020-04-28 6:32 ` [PATCH v2 3/6] irqchip: Add Loongson PCH PIC controller Jiaxun Yang
2020-05-13 12:09 ` Thomas Gleixner [this message]
2020-04-28 6:32 ` [PATCH v2 4/6] dt-bindings: interrupt-controller: Add Loongson PCH PIC Jiaxun Yang
2020-04-28 6:32 ` [PATCH v2 5/6] irqchip: Add Loongson PCH MSI controller Jiaxun Yang
2020-04-28 13:07 ` Marc Zyngier
2020-05-13 12:13 ` Thomas Gleixner
2020-05-13 12:15 ` Thomas Gleixner
2020-05-20 11:51 ` Jiaxun Yang
2020-04-28 6:32 ` [PATCH v2 6/6] dt-bindings: interrupt-controller: Add Loongson PCH MSI Jiaxun Yang
2020-04-28 16:59 ` [PATCH v2 1/6] irqchip: Add Loongson HyperTransport Vector support Marc Zyngier
2020-05-01 9:21 ` [PATCH v3 " Jiaxun Yang
2020-05-01 9:21 ` [PATCH v3 2/6] dt-bindings: interrupt-controller: Add Loongson HTVEC Jiaxun Yang
2020-05-12 16:42 ` Rob Herring
2020-05-01 9:21 ` [PATCH v3 3/6] irqchip: Add Loongson PCH PIC controller Jiaxun Yang
2020-05-01 9:21 ` [PATCH v3 4/6] dt-bindings: interrupt-controller: Add Loongson PCH PIC Jiaxun Yang
2020-05-01 9:21 ` [PATCH v3 5/6] irqchip: Add Loongson PCH MSI controller Jiaxun Yang
2020-05-01 9:21 ` [PATCH v3 6/6] dt-bindings: interrupt-controller: Add Loongson PCH MSI Jiaxun Yang
2020-05-12 20:57 ` Rob Herring
2020-05-12 7:45 ` [PATCH v3 1/6] irqchip: Add Loongson HyperTransport Vector support Jiaxun Yang
2020-05-13 12:06 ` Thomas Gleixner
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